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LTC3855 3855f typical a pplica t ion descrip t ion dual, multiphase synchronous dc/dc controller with differential remote sense the ltc ? 3855 is a dual polyphase ? current mode synchro- nous step-down switching regulator controller that drives all n-channel power mosfet stages. it includes a high speed differential remote sense amplifer. the maximum current sense voltage is programmable for either 30mv, 50mv or 75mv, allowing the use of either the inductor dcr or a discrete sense resistor as the sensing element. the LTC3855 features a precision 0.6v reference and can produce output voltages up to 12.5v. a wide 4.5v to 38v input supply range encompasses most intermediate bus voltages and battery chemistries. power loss and supply noise are minimized by operating the two controller output stages out of phase. burst mode ? operation, continuous or pulse-skipping modes are supported. the LTC3855 can be confgured for up to 12-phase op- eration, has dcr temperature compensation, two power good signals and two current limit set pins. the LTC3855 is available in low profle 40-pin 6mm 6mm qfn and 38-lead exposed pad fe packages. l , lt, ltc, ltm, linear technology, the linear logo, burst mode and polyphase are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners. protected by u.s. patents including 5481178, 5705919, 5929620, 6100678, 6144194, 6177787, 6304066, 6580258. fea t ures a pplica t ions n dual, 180 phased controllers reduce required input capacitance and power supply induced noise n high effciency: up to 95% n r sense or dcr current sensing n programmable dcr temperature compensation n 0.75% 0.6v output voltage accuracy n phase-lockable fixed frequency 250khz to 770khz n true remote sensing differential amplifer n dual n-channel mosfet synchronous drive n wide v in range: 4.5v to 38v n v out range: 0.6v to 12.5v without differential amplifer n v out range: 0.6v to 3.3v with differential amplifer n clock input and output for up to 12-phase operation n adjustable soft-start or v out tracking n foldback output current limiting n output overvoltage protection n 40-pin (6mm 6mm) qfn and 38-lead fe packages n computer systems n telecom systems n industrial and medical instruments n dc power distribution systems high effciency dual 1.8v/1.2v step-down converter 0.1f 40.2k 0.56h 470pf 1f 22f 330f 2 20k 15k v out1 1.8v 15a 0.1f 0.4h 470pf 330f 2 20k 7.5k 100k v out2 1.2v 15a tg1 tg2 boost1 boost2 sw1 sw2 bg1 bg2 diffp pgnd2 freq sense1 + sense2 + diffout sense1 ? sense2 ? v fb1 v fb2 i th1 i th2 v in intv cc tk/ss1 tk/ss2 v in 4.5v to 20v 3855 ta01 diffn sgnd 0.1f 0.1f LTC3855 pgnd1 4.7f + + + 20k load step (forced continuous mode) v in = 12v v out = 1.8v 50s/div 3855 ta01a i l 5a/div v out 100mv/div ac-coupled i load 5a/div 300ma to 5a
LTC3855 3855f a bsolu t e maxi m u m r a t ings (note 1) p in c on f igura t ion input supply voltage (v in ) ......................... C 0.3v to 40v top side driver voltages boost1, boost2 .................................. C 0.3v to 46v switch voltage (sw1, sw2) ......................... C 5v to 40v intv cc , run1, run2, pgood(s), extv cc , (boost1-sw1), (boost2-sw2) ............. C 0.3v to 6v sense1 + , sense2 + , sense1 C , sense2 C voltages ................................. C 0.3v to 13v mode/pllin, i lim1 , i lim2 , tk/ss1, tk/ss2, freq, diffout, phasmd voltages ............. C 0.3v to intv cc diffp, diffn .......................................... C 0.3v to intv cc itemp1, itemp2 voltages .................... C 0.3v to intv cc i th1 , i th2 , v fb1 , v fb2 voltages .............. C 0.3v to intv cc intv cc peak output current (note 8) ..................100ma operating junction temperature range (notes 2, 3) LTC3855 .............................................C 40c to 125c storage temperature range ...................C65c to 125c lead temperature (soldering, 10 sec) (fe package) ..................................................... 300c 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 top view fe package 38-lead plastic ssop 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 itemp2 itemp1 run1 sense1 + sense1 ? tk/ss1 i th1 v fb1 v fb2 i th2 tk/ss2 sense2 + sense2 ? diffp diffn diffout run2 i lim1 i lim2 freq mode/pllin phasmd clkout sw1 tg1 boost1 pgnd1 bg1 v in intv cc extv cc bg2 pgnd2 boost2 tg2 sw2 pgood2 pgood1 39 sgnd t jmax = 125c, ja = 25c/w exposed pad (pin 39) is sgnd, must be soldered to pcb 39 40 38 37 36 35 34 33 32 31 11 20 12 13 14 15 top view 41 sgnd uj package 40-lead (6mm s 6mm) plastic qfn 16 17 18 19 22 23 24 25 26 27 28 29 9 8 7 6 5 4 3 2 tk/ss1 i th1 v fb1 sgnd v fb2 i th2 tk/ss2 sense2 + sense2 ? diffp tg1 boost1 pgnd1 bg1 v in intv cc extv cc bg2 pgnd2 boost2 sense1 ? sense1 + run1 itemp1 itemp2 freq mode/pllin phasmd clkout sw1 diffn diffout run2 i lim1 i lim2 pgood1 pgood2 nc sw2 tg2 21 30 10 1 t jmax = 125c, ja = 33c/w exposed pad (pin 41) is sgnd, must be soldered to pcb
LTC3855 3855f o r d er in f or m a t ion lead free finish tape and reel part marking* package description temperature range LTC3855efe#pbf LTC3855efe#trpbf LTC3855fe 38-lead plastic tssop C40c to 85c LTC3855ife#pbf LTC3855ife#trpbf LTC3855fe 38-lead plastic tssop C40c to 125c LTC3855euj#pbf LTC3855euj#trpbf LTC3855uj 40-lead (6mm 6mm) plastic qfn C40c to 85c LTC3855iuj#pbf LTC3855iuj#trpbf LTC3855uj 40-lead (6mm 6mm) plastic qfn C40c to 125c consult ltc marketing for parts specifed with wider operating temperature ranges. *the temperature grade is identifed by a label on the shipping container. consult ltc marketing for information on non-standard lead based fnish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifcations, go to: http://www.linear.com/tapeandreel/ symbol parameter conditions min typ max units main control loops v in input voltage range 4.5 38 v v out output voltage range 0.6 12.5 v v fb1,2 regulated feedback voltage i th1,2 voltage = 1.2v (note 4) i th1,2 voltage = 1.2v (note 4), t a = 125c l l 0.5955 0.594 0.600 0.600 0.6045 0.606 v v i fb1,2 feedback current (note 4) C15 C50 na v reflnreg reference voltage line regulation v in = 4.5v to 38v (note 4) 0.002 0.02 %/v v loadreg output voltage load regulation (note 4) measured in servo loop; ?i th voltage = 1.2v to 0.7v measured in servo loop; ?i th voltage = 1.2v to 1.6v l l 0.01 C0.01 0.1 C0.1 % % g m1,2 transconductance amplifer g m i th1,2 = 1.2v; sink/source 5a; (note 4) 2 mmho i q input dc supply current normal mode shutdown (note 5) v in = 15v v run1,2 = 0v 3.5 30 50 ma a df max maximum duty factor in dropout, f osc = 500khz 94 95 % uvlo undervoltage lockout v intvcc ramping down l 3.0 3.2 3.4 v uvlo hys uvlo hysteresis 0.6 v v ovl1,2 feedback overvoltage lockout measured at v fb1,2 l 0.64 0.66 0.68 v i sense1,2 sense pins bias current (each channel); v sense1,2 = 3.3v l 1 2 a i temp1,2 dcr tempco compensation current v itemp1,2 = 0.2v l 9 10 11 a i tk/ss1,2 soft-start charge current v tk/ss1,2 = 0v l 1 1.2 1.4 a v run1,2 run pin on threshold v run1 , v run2 rising l 1.1 1.22 1.35 v v run1,2hys run pin on hysteresis 80 mv v sense(max) maximum current sense threshold v fb1,2 = 0.5v, v sense1,2 = 3.3v, i lim = 0v v fb1,2 = 0.5v, v sense1,2 = 3.3v, i lim = float v fb1,2 = 0.5v, v sense1,2 = 3.3v, i lim = intv cc l l l 25 45 68 30 50 75 35 55 82 mv mv mv tg1, 2 t r tg1, 2 t f tg transition time: rise time fall time (note 6) c load = 3300pf c load = 3300pf 25 25 ns ns bg1, 2 t r bg1, 2 t f bg transition time: rise time fall time (note 6) c load = 3300pf c load = 3300pf 25 25 ns ns e lec t rical c harac t eris t ics the l denotes the specifcations which apply over the full operating junction temperature range (e-grade), otherwise specifcations are at t a = 25c. v in = 15v, v run1,2 = 5v unless otherwise noted.
LTC3855 3855f symbol parameter conditions min typ max units tg/bg t 1d top gate off to bottom gate on delay synchronous switch-on delay time c load = 3300pf each driver 30 ns bg/tg t 2d bottom gate off to top gate on delay top switch-on delay time c load = 3300pf each driver 30 ns t on(min) minimum on-time (note 7) 90 ns intv cc linear regulator v intvcc internal v cc voltage 6v < v in < 38v 4.8 5 5.2 v v ldo int intv cc load regulation i cc = 0ma to 20ma 0.5 2 % v extvcc extv cc switchover voltage extv cc ramping positive l 4.5 4.7 v v ldo ext extv cc voltage drop i cc = 20ma, v extvcc = 5v 50 100 mv v ldohys extv cc hysteresis 200 mv oscillator and phase-locked loop f nom nominal frequency v freq = 1.2v 450 500 550 khz f low lowest frequency v freq = 0v 210 250 290 khz f high highest frequency v freq 2.4v 700 770 850 khz r mode/pllin mode/pllin input resistance 250 k? i freq frequency setting current 9 10 11 a clkout phase (relative to controller 1) phasmd = gnd phasmd = float phasmd = intv cc 60 90 120 deg deg deg clk high clock high output voltage 4 5 v clk low clock low output voltage 0 0.2 v pgood output v pgl pgood voltage low i pgood = 2ma 0.1 0.3 v i pgood pgood leakage current v pgood = 5v 2 a v pg pgood trip level, either controller v fb with respect to set output voltage v fb ramping negative v fb ramping positive C10 10 % % differential amplifer a da gain l 0.998 1 1.002 v/v r in input resistance measured at diffp input 80 k v os input offset voltage v diffp = v diffout = 1.5v, i diffout = 100a 2 mv psrr oa power supply rejection ratio 5v < v in < 38v 100 db i cl maximum output current 2 3 ma v out(max) maximum output voltage i diffout = 300a v intvcc C 1.4 v intvcc C 1.1 v gbw gain bandwidth product (note 8) 3 mhz slew rate differential amplifer slew rate (note 8) 2 v/s e lec t rical c harac t eris t ics the l denotes the specifcations which apply over the full operating junction temperature range (e-grade), otherwise specifcations are at t a = 25c. v in = 15v, v run1,2 = 5v unless otherwise noted.
LTC3855 3855f note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: the LTC3855e is guaranteed to meet performance specifcations from 0c to 85c. specifcations over the C40c to 85c operating junction temperature range are assured by design, characterization and correlation with statistical process controls. the LTC3855i is guaranteed to meet performance specifcations over the full C40c to 125c operating junction temperature range. note 3: t j is calculated from the ambient temperature t a and power dissipation p d according to the following formulas: LTC3855uj: t j = t a + (p d ? 33c/w) LTC3855fe: t j = t a + (p d ? 25c/w) e lec t rical c harac t eris t ics the l denotes the specifcations which apply over the full operating junction temperature range (e-grade), otherwise specifcations are at t a = 25c. v in = 15v, v run/ss = 5v unless otherwise noted. note 4: the LTC3855 is tested in a feedback loop that servos v ith1,2 to a specifed voltage and measures the resultant v fb1,2 . note 5: dynamic supply current is higher due to the gate charge being delivered at the switching frequency. see applications information. note 6: rise and fall times are measured using 10% and 90% levels. delay times are measured using 50% levels. note 7: the minimum on-time condition is specifed for an inductor peak-to-peak ripple current 40% of i max (see minimum on-time considerations in the applications information section). note 8: guaranteed by design. symbol parameter conditions min typ max units on chip driver tg r up tg pull-up r ds(on) tg high 2.6 tg r down tg pull-down r ds(on) tg low 1.5 bg r up bg pull-up r ds(on) bg high 2.4 bg r down bg pull-down r ds(on) bg low 1.1 typical p er f or m ance c harac t eris t ics effciency vs output current and mode effciency vs output current and mode load current (a) 0.01 efficiency (%) 100 10 90 70 50 30 80 60 40 20 0 10 3855 g23 100 1 0.1 v in = 12v v out = 1.8v burst mode operation dcm ccm circuit of figure 19 load current (a) 0.01 efficiency (%) 100 10 90 70 50 30 80 60 40 20 0 10 3855 g24 100 1 0.1 v in = 12v v out = 1.2v burst mode operation dcm ccm circuit of figure 19 full load effciency and power loss vs input voltage input voltage (v) 5 75 efficiency (%) 80 85 90 2 power loss (w) 3 4 5 10 20 15 3855 g24 1.8v 1.8v 1.2v 1.2v efficiency power loss circuit of figure 19
LTC3855 3855f typical p er f or m ance c harac t eris t ics load step (burst mode operation) load step (forced continuous mode) load step (pulse-skipping mode) inductor current at light load coincident tracking prebiased output at 2v v in = 12v v out = 1.8v 50s/div 3855 g01 i l 5a/div v out 100mv/div ac-coupled i load 5a/div 300ma to 5a v in = 12v v out = 1.8v 50s/div 3855 g02 i l 5a/div v out 100mv/div ac-coupled i load 5a/div 300ma to 5a v in = 12v v out = 1.8v 50s/div 3855 g03 i l 5a/div v out 100mv/div ac-coupled i load 5a/div 300ma to 5a v in = 12v v out = 1.8v i load = 400ma 1s/div 3855 g04 forced continuous mode 5a/div burst mode operation 5a/div pulse-skipping mode 5a/div v in = 12v v out = 3.3v 2ms/div 3855 g05 tk/ss 500mv/div v fb 500mv/div v out 2v/div 5ms/div 3855 g06 run 2v/div v out1 v out2 1v/div v out1 v out2 v out1 = 1.8v, 1.5 load v out2 = 1.2v, 1 load
LTC3855 3855f v ith (v) 0 ?40 v sense (mv) ?20 0 20 40 60 80 0.5 1 1.5 2 3855 g10 i lim = gnd i lim = float i lim = intv cc v sense common mode voltage (v) 0 current sense threshold (mv) 30 40 50 12 20 10 0 2 6 8 10 4 60 70 80 3855 g11 i lim = gnd i lim = float i lim = intv cc 60 80 40 20 50 70 30 10 0 duty cycle (%) 0 current sense threshold (mv) 60 100 20 40 80 3855 g12 i lim = gnd i lim = float i lim = intv cc typical p er f or m ance c harac t eris t ics current sense threshold vs i th voltage maximum current sense threshold vs common mode voltage maximum current sense threshold vs duty cycle maximum current sense voltage vs feedback voltage (current foldback) tk/ss pull-up current vs temperature tracking up and down with external ramp quiescent current vs temperature without extv cc intv cc line regulation v in = 12v v out1 = 1.8v, 1.5 load v out2 = 1.2v, 1 load 10ms/div 3855 g07 tk/ss1 tk/ss2 2v/div v out1 v out2 500ma/div v out1 v out2 quiescent current (ma) 4.5 4.0 3.0 2.0 1.0 3.5 2.5 1.5 0.5 0 temperature (c) ?50 50 0 100 3855 g08 125 25 ?25 75 intv cc voltage (v) 5.5 5.0 4.5 4.0 3.0 3.5 2.5 2.0 input voltage (v) 0 10 30 3855 g09 40 20 feedback voltage (v) 0 maximum current sense threshold (mv) 30 40 50 0.6 20 10 0 0.1 0.3 0.4 0.5 0.2 60 70 90 80 3855 g13 i lim = gnd i lim = float i lim = intv cc tk/ss current (a) 1.6 1.2 1.4 1.0 temperature (c) ?50 50 0 100 3855 g14 125 25 ?25 75
LTC3855 3855f typical p er f or m ance c harac t eris t ics undervoltage lockout threshold (intv cc ) vs temperature oscillator frequency vs input voltage shutdown current vs input voltage shutdown current vs temperature quiescent current vs input voltage without extv cc shutdown (run) threshold vs temperature regulated feedback voltage vs temperature oscillator frequency vs temperature temperature (c) ?50 1.26 1.24 1.22 1.20 1.14 1.18 1.16 1.12 1.10 25 75 3855 g15 ?25 0 50 125100 run pin threshold (v) off on temperature (c) ?50 612 610 608 606 604 602 600 592 594 596 598 25 75 3855 g16 ?25 0 50 125100 regulated feedback voltage (mv) temperature (c) ?50 900 800 700 500 600 0 100 200 300 400 25 75 3855 g17 ?25 0 50 125100 frequency (khz) v freq = gnd v freq = 1.2v v freq = intv cc temperature (c) ?40 4.1 3.9 2.9 3.7 2.7 3.1 3.5 2.5 3.3 20 60 3855 g18 ?20 0 40 10080 uvlo threshold (v) falling rising input voltage (v) 5 520 510 500 490 480 25 35 3855 g19 10 15 20 40 30 frequency (khz) input voltage (v) 5 60 50 40 30 20 10 0 25 35 3855 g20 10 15 20 40 30 shutdown input current (a) 60 50 40 30 20 10 0 3855 g21 shutdown current (a) temperature (c) ?50 25 75 ?25 0 50 125100 input voltage (v) 5 4.5 4.3 4.1 3.3 3.1 2.5 2.7 2.9 3.5 3.7 3.9 25 35 3855 g22 10 15 20 40 30 supply current (ma)
LTC3855 3855f p in func t ions itemp1, itemp2 (pin 2, pin 1/pin 37, pin 36): inputs of the temperature sensing comparators. connect each of these pins to external ntc resistors placed near induc- tors. floating these pins disables the dcr temperature compensation function. run1, run2 (pin 3, pin 17/pin 38, pin 13): run control inputs. a voltage above 1.2v on either pin turns on the ic. however, forcing either of these pins below 1.2v causes the ic to shut down the circuitry required for that particular channel. there are 1a pull-up currents for these pins. once the run pin rises above 1.2v, an additional 4.5a pull-up current is added to the pin. sense1 + , sense2 + (pin 4, pin 12/pin 39, pin 8): current sense comparator inputs. the (+) inputs to the current comparators are normally connected to dcr sensing networks or current sensing resistors. sense1 C , sense2 C (pin 5, pin 13/pin 40, pin 9): current sense comparator inputs. the (C) inputs to the current comparators are connected to the outputs. tk/ss1, tk/ss2 (pin 6, pin 11/pin 1, pin 7): output volt- age tracking and soft-start inputs. when one particular channel is confgured to be the master of two channels, a capacitor to ground at this pin sets the ramp rate for the master channels output voltage. when the channel is confgured to be the slave of two channels, the v fb voltage of the master channel is reproduced by a resistor divider and applied to this pin. internal soft-start currents of 1.2a are charging these pins. i th1 , i th2 (pin 7, pin 10/pin 2, pin 6): current control thresholds and error amplifer compensation points. each associated channels current comparator tripping threshold increases with its i th control voltage. v fb1 , v fb2 (pin 8, pin 9/pin 3, pin 5): error amplifer feedback inputs. these pins receive the remotely sensed feedback voltages for each channel from external resistive dividers across the outputs. diffp (pin 14/pin 10): positive input of remote sens- ing differential amplifer. connect this to the remote load voltage of one of the two channels directly. diffn (pin 15/pin 11): negative input of remote sensing differential amplifer. connect this to the negative terminal of the output capacitors. diffout (pin 16/pin 12): output of remote sensing dif- ferential amplifer. connect this to v fb1 or v fb2 through a resistive divider. i lim1 , i lim2 (pin 18, pin 19/pin 14, pin 15): current comparator sense voltage range inputs. this pin can be tied to sgnd, tied to intv cc or left foating to set the maximum current sense threshold for each comparator. pgood1, pgood2 (pin 20, pin 21/pin 16, pin 17): power good indicator output for each channel. open drain logic out that is pulled to ground when either channel output exceeds 10% regulation window, after the internal 20s power bad mask timer expires. extv cc (pin 27/pin 24): external power input to an inter- nal switch connected to intv cc . this switch closes and supplies the ic power, bypassing the internal low dropout regulator, whenever extv cc is higher than 4.7v. do not exceed 6v on this pin. intv cc (pin 28/pin 25): internal 5v regulator output. the control circuits are powered from this voltage. decouple this pin to pgnd with a minimum of 4.7f low esr tan- talum or ceramic capacitor. v in (pin 29/pin 26): main input supply. decouple this pin to pgnd with a capacitor (0.1f to 1f). bg1, bg2 (pin 30, pin 26/pin 27, pin 23): bottom gate driver outputs. these pins drive the gates of the bottom n-channel mosfets between pgnd and intv cc . pgnd1, pgnd2 (pin 31, pin 25/pin 28, pin 22): power ground pin. connect this pin closely to the sources of the bottom n-channel mosfets, the (C) terminal of c vcc and the (C) terminal of c in . (fe38/uj40)
LTC3855 0 3855f p in func t ions boost1, boost2 (pin 32, pin 24/pin 29, pin 21): boosted floating driver supplies. the (+) terminal of the bootstrap capacitors connect to these pins. these pins swing from a diode voltage drop below intv cc up to v in + intv cc . tg1, tg2 (pin 33, pin 23/pin 30, pin 20): top gate driver outputs. these are the outputs of foating drivers with a voltage swing equal to intv cc superimposed on the switch nodes voltages. sw1, sw2 (pin 34, pin 22/pin 31, pin 19): switch node connections to inductors. voltage swing at these pins is from a schottky diode (external) voltage drop below ground to v in . phasmd (pin 36/pin 33): this pin can be tied to sgnd, tied to intv cc or left foating. this pin determines the relative phases between the internal controllers as well as the phasing of the clkout signal. see table 1 in the operation section. clkout (pin 35/pin 32): clock output with phase change- able by phasmd to enable usage of multiple LTC3855 in multiphase systems. mode/pllin (pin 37/pin 34): this is a dual purpose pin. when external frequency synchronization is not used, this pin selects the operating mode. the pin can be tied to sgnd, tied to intv cc or left foating. sgnd enables forced continuous mode. intv cc enables pulse-skipping mode. floating enables burst mode operation. for external sync, apply a clock signal to this pin. both channels will go into forced continuous mode and the internal pll will synchronize the internal oscillator to the clock. the pll compensation network is integrated into the ic. freq (pin 38/pin 35): there is a precision 10a current fowing out of this pin. a resistor to ground sets a voltage which in turn programs the frequency. alternatively, this pin can be driven with a dc voltage to vary the frequency of the internal oscillator. sgnd (exposed pad pin 39/ pin 4, exposed pad pin 41): signal ground. all small-signal components and com- pensation components should connect to this ground, which in turn connects to pgnd at one point. exposed pad must be soldered to pcb, providing a local ground for the control components of the ic, and be tied to the pgnd pin under the ic. (fe38/uj40)
LTC3855 3855f func t ional b lock diagra m 4.7v ? + ? + ? + v in 1 a slope compensation uvlo slope recovery active clamp osc tempsns s r q 3k run switch logic and anti- shoot through bg on fcnt 0.6v ov 1.2v 0.5v i th r c intv cc intv cc i lim i cmp c c1 ss sgnd r1 0.66v r2 run pgnd pgood intv cc extv cc i rev sw tg c b v in c in v in sleep boost bursten ? + ? + uv ov c vcc v out c out m2 m1 l1 d b mode/pllin sense + sense ? ? + 0.6v ref tk/ss run 0.55v ? + v fb freq pll-sync mode/sync detect 40k 40k 40k 40k + 5v reg 1.2 a c ss + diffp diffn ? + ? + f f clkout 0.54v ? + diffout phasmd itemp 3855 fbd 1 51k i thb ? + ea + diffamp
LTC3855 3855f o pera t ion main control loop the LTC3855 is a constant-frequency, current mode step- down controller with two channels operating 180 degrees out-of-phase. during normal operation, each top mosfet is turned on when the clock for that channel sets the rs latch, and turned off when the main current comparator, i cmp , resets the rs latch. the peak inductor current at which i cmp resets the rs latch is controlled by the voltage on the i th pin, which is the output of each error ampli- fer ea. the v fb pin receives the voltage feedback signal, which is compared to the internal reference voltage by the ea. when the load current increases, it causes a slight decrease in v fb relative to the 0.6v reference, which in turn causes the i th voltage to increase until the average inductor current matches the new load current. after the top mosfet has turned off, the bottom mosfet is turned on until either the inductor current starts to reverse, as indicated by the reverse current comparator i rev , or the beginning of the next cycle. intv cc /extv cc power power for the top and bottom mosfet drivers and most other internal circuitry is derived from the intv cc pin. when the extv cc pin is left open or tied to a voltage less than 4.7v, an internal 5v linear regulator supplies intv cc power from v in . if extv cc is taken above 4.7v, the 5v regulator is turned off and an internal switch is turned on connecting extv cc . using the extv cc pin allows the intv cc power to be derived from a high effciency external source such as one of the LTC3855 switching regulator outputs. each top mosfet driver is biased from the foating bootstrap capacitor c b , which normally recharges during each off cycle through an external diode when the top mosfet turns off. if the input voltage v in decreases to a voltage close to v out , the loop may enter dropout and attempt to turn on the top mosfet continuously. the dropout detector detects this and forces the top mosfet off for about one-twelfth of the clock period plus 100ns every third cycle to allow c b to recharge. however, it is recommended that a load be present or the ic operates at low frequency during the drop-out transition to ensure c b is recharged. shutdown and start-up (run1, run2 and tk/ss1, tk/ss2 pins) the two channels of the LTC3855 can be independently shut down using the run1 and run2 pins. pulling either of these pins below 1.2v shuts down the main control loop for that controller. pulling both pins low disables both controllers and most internal circuits, including the intv cc regulator. releasing either run pin allows an internal 1a current to pull up the pin and enable that controller. alternatively, the run pin may be externally pulled up or driven directly by logic. be careful not to exceed the absolute maximum rating of 6v on this pin. the start-up of each controllers output voltage v out is controlled by the voltage on the tk/ss1 and tk/ss2 pins. when the voltage on the tk/ss pin is less than the 0.6v internal reference, the LTC3855 regulates the v fb voltage to the tk/ss pin voltage instead of the 0.6v reference. this allows the tk/ss pin to be used to program the soft-start period by connecting an external capacitor from the tk/ss pin to sgnd. an internal 1.2a pull-up current charges this capacitor, creating a voltage ramp on the tk/ss pin. as the tk/ss voltage rises linearly from 0v to 0.6v (and beyond), the output voltage v out rises smoothly from zero to its fnal value. alternatively the tk/ss pin can be used to cause the start-up of v out to track that of another supply. typically, this requires connecting to the tk/ss pin an external resistor divider from the other supply to ground (see the applications information section). when the corresponding run pin is pulled low to disable a controller, or when intv cc drops below its undervoltage lockout threshold of 3.2v, the tk/ss pin is pulled low by an internal mosfet. when in undervoltage lockout, both controllers are disabled and the external mosfets are held off. light load current operation (burst mode operation, pulse-skipping, or continuous conduction) the LTC3855 can be enabled to enter high effciency burst mode operation, constant-frequency pulse-skipping mode, or forced continuous conduction mode. to select forced continuous operation, tie the mode/pllin pin to a dc
LTC3855 3855f voltage below 0.6v (e.g., sgnd). to select pulse-skipping mode of operation, tie the mode/pllin pin to intv cc . to select burst mode operation, foat the mode/pllin pin. when a controller is enabled for burst mode operation, the peak current in the inductor is set to approximately one-third of the maximum sense voltage even though the voltage on the i th pin indicates a lower value. if the average inductor current is higher than the load current, the error amplifer ea will decrease the voltage on the i th pin. when the i th voltage drops below 0.5v, the internal sleep signal goes high (enabling sleep mode) and both external mosfets are turned off. in sleep mode, the load current is supplied by the output capacitor. as the output voltage decreases, the eas output begins to rise. when the output voltage drops enough, the sleep signal goes low, and the controller resumes normal operation by turning on the top external mosfet on the next cycle of the internal oscillator. when a controller is enabled for burst mode operation, the inductor current is not allowed to reverse. the reverse current comparator (i rev ) turns off the bottom external mosfet just before the inductor current reaches zero, preventing it from reversing and going negative. thus, the controller oper- ates in discontinuous operation. in forced continuous operation, the inductor current is allowed to reverse at light loads or under large transient conditions. the peak inductor current is determined by the voltage on the i th pin. in this mode, the effciency at light loads is lower than in burst mode operation. however, continuous mode has the advantages of lower output ripple and less interference with audio circuitry. when the mode/pllin pin is connected to intv cc , the LTC3855 operates in pwm pulse-skipping mode at light loads. at very light loads, the current comparator i cmp may remain tripped for several cycles and force the external top mosfet to stay off for the same number of cycles (i.e., skipping pulses). the inductor current is not allowed to reverse (discontinuous operation). this mode, like forced continuous operation, exhibits low output ripple as well as low audio noise and reduced rf interference as compared to burst mode operation. it provides higher low current effciency than forced continuous mode, but not nearly as high as burst mode operation. multichip operations (phasmd and clkout pins) the phasmd pin determines the relative phases between the internal controllers as well as the clkout signal as shown in table 1. the phases tabulated are relative to zero phase being defned as the rising edge of the clock of phase 1. table 1. phasmd gnd float intvcc phase1 0 0 0 phase2 180 180 240 clkout 60 90 120 the clkout signal can be used to synchronize additional power stages in a multiphase power supply solution feeding a single, high current output or separate outputs. input capacitance esr requirements and effciency losses are substantially reduced because the peak current drawn from the input capacitor is effectively divided by the number of phases used and power loss is proportional to the rms current squared. a two stage, single output voltage implementation can reduce input path power loss by 75% and radically reduce the required rms current rating of the input capacitor(s). single output multiphase operation the LTC3855 can be used for single output multiphase converters by making these connections ? t ie all of the i th pins together ? tie all of the v fb pins together ? tie all of the tk/ss pins together ? tie all of the run pins together ? tie all of the itemp pins together ? tie all of the i lim pins together, or tie the i lim pins to the same potential for three or more phases, tie the inputs of the unused dif- ferential amplifer(s) to ground. examples of single output multiphase converters are shown in figures 20 to 23. o pera t ion
LTC3855 3855f sensing the output voltage with a differential amplifer the LTC3855 includes a low offset, unity gain, high band- width differential amplifer for applications that require true remote sensing. sensing the load across the load capaci- tors directly greatly benefts regulation in high current, low voltage applications, where board interconnection losses can be a signifcant portion of the total error budget. the LTC3855 differential amplifer has a typical output slew rate of 2v/s. the amplifer is confgured for unity gain, meaning that the difference between diffp and diffn is translated to diffout, relative to sgnd. care should be taken to route the diffp and diffn pcb traces parallel to each other all the way to the terminals of the output capacitor or remote sensing points on the board. in addition, avoid routing these sensitive traces near any high speed switching nodes in the circuit. ideally, the diffp and diffn traces should be shielded by a low impedance ground plane to maintain signal integrity. inductor dcr sensing temperature compensation and the itemp pins inductor dcr current sensing provides a lossless method of sensing the instantaneous current. therefore, it can provide higher effciency for applications of high output currents. however the dcr of a copper inductor typically has a positive temperature coeffcient. as the temperature of the inductor rises, its dcr value increases. the current limit of the controller is therefore reduced. LTC3855 offers a method to counter this inaccuracy by allowing the user to place an ntc temperature sensing resistor near the inductor. itemp pin, when left foating, is at a voltage around 5v and dcr temperature compensa- tion is disabled. itemp pin has a constant 10a precision current fowing out the pin. by connecting an ntc resistor from itemp pin to sgnd, the maximum current sense threshold can be varied over temperature according the following equation: v v v sensemax adj sense max itemp ( ) ( ) ? . ? . = 1 8 1 3 where: v sensemax(adj) is the maximum adjusted current sense threshold. v sense(max) is the maximum current sense threshold specifed in the electrical characteristics table. it is typi- cally 75mv, 50mv, or 30mv depending on the setting i lim pins. v itemp is the voltage of itemp pin. the valid voltage range for dcr temperature compensa- tion on the itemp pin is between 0.5v to 0.2v, with 0.5v or above being no dcr temperature correction and 0.2v the maximum correction. however, if the duty cycle of the controller is less than 25%, the itemp range is extended from 0.5v to 0v. an ntc resistor has a negative temperature coeffcient, that means that its value decreases as temperature rises. the v itemp voltage, therefore, decreases as temperature increases and in turn the v sensemax(adj) will increase to compensate the dcr temperature coeffcient. the ntc resistor, however, is non-linear and user can linearize its value by building a resistor network with regular resis- tors. consult the ntc manufacture datasheets for detailed information. another use for the itemp pins, in addition to ntc com- pensated dcr sensing, is adjusting v sense(max) to values between the nominal values of 30mv, 50mv and 75mv for a more precise current limit. this is done by applying a voltage less than 0.5v to the itemp pin. v sense(max) will be varied per the above equation and the same duty cycle limitations will apply. the current limit can be adjusted using this method either with a sense resistor or dcr sensing. for more information see the ntc compensated dcr sens- ing paragraph in the applications information section. frequency selection and phase-locked loop (freq and mode/pllin pins) the selection of switching frequency is a trade-off between effciency and component size. low frequency opera- tion increases effciency by reducing mosfet switching losses, but requires larger inductance and/or capacitance to maintain low output ripple voltage. the switching o pera t ion
LTC3855 3855f frequency of the LTC3855s controllers can be selected using the freq pin. if the mode/pllin pin is not being driven by an external clock source, the freq pin can be used to program the controllers operating frequency from 250khz to 770khz. there is a precision 10a current fowing out of the freq pin, so the user can program the controllers switching frequency with a single resistor to sgnd. a curve is provided later in the application section showing the relationship between the voltage on the freq pin and switching frequency. a phase-locked loop (pll) is integrated on the LTC3855 to synchronize the internal oscillator to an external clock source that is connected to the mode/pllin pin. the controller is operating in forced continuous mode when it is synchronized. the pll loop flter network is integrated inside the LTC3855. the phase-locked loop is capable of locking any frequency within the range of 250khz to 770khz. the frequency setting resistor should always be present to set the controllers initial switching frequency before locking to the external clock. o pera t ion power good (pgood pins) when v fb pin voltage is not within 10% of the 0.6v refer- ence voltage, the pgood pin is pulled low. the pgood pin is also pulled low when the run pin is below 1.2v or when the LTC3855 is in the soft-start or tracking phase. the pgood pin will fag power good immediately when the v fb pin is within the 10% of the reference window. however, there is an internal 20s power bad mask when v fb goes out the 10% window. each channel has its own pgood and only responds to its own channel signals. the pgood pins are allowed to be pulled up by external resistors to sources of up to 6v. output overvoltage protection an overvoltage comparator, ov, guards against transient overshoots (>10%) as well as other more serious condi- tions that may overvoltage the output. in such cases, the top mosfet is turned off and the bottom mosfet is turned on until the overvoltage condition is cleared. a pplica t ions i n f or m a t ion the typical application on the frst page is a basic LTC3855 application circuit. LTC3855 can be confgured to use either dcr (inductor resistance) sensing or low value resistor sensing. the choice between the two current sensing schemes is largely a design trade-off between cost, power consumption, and accuracy. dcr sensing is becoming popular because it saves expensive current sensing resis- tors and is more power effcient, especially in high current applications. however, current sensing resistors provide the most accurate current limits for the controller. other external component selection is driven by the load require- ment, and begins with the selection of r sense (if r sense is used) and inductor value. next, the power mosfets are se- lected. finally, input and output capacitors are selected. current limit programming the i lim pin is a tri-level logic input which sets the maxi- mum current limit of the controller. when i lim is either grounded, foated or tied to intv cc , the typical value for the maximum current sense threshold will be 30mv, 50mv or 75mv, respectively. the maximum current sense threshold will be adjusted to values between these settings by applying a voltage less than 0.5v to the itemp pin. see the operation section for more details. which setting should be used? for the best current limit accuracy, use the 75mv setting. the 30mv setting will allow for the use of very low dcr inductors or sense resistors, but at the expense of current limit accuracy. the 50mv setting is a good balance between the two. for single output dual phase applications, use the 50mv or 75mv setting for optimal current sharing. sense + and sense C pins the sense + and sense C pins are the inputs to the current comparators. the common mode input voltage range of the current comparators is 0v to 12.5v. both sense pins are high impedance inputs with small base currents of
LTC3855 3855f less than 1a. when the sense pins ramp up from 0v to 1.4v, the small base currents fow out of the sense pins. when the sense pins ramp down from 12.5v to 1.1v, the small base currents fow into the sense pins. the high impedance inputs to the current comparators allow accurate dcr sensing. however, care must be taken not to foat these pins during normal operation. filter components mutual to the sense lines should be placed close to the LTC3855, and the sense lines should run close together to a kelvin connection underneath the current sense element (shown in figure 1). sensing cur- rent elsewhere can effectively add parasitic inductance and capacitance to the current sense element, degrading the information at the sense terminals and making the programmed current limit unpredictable. if dcr sensing is used (figure 2b), sense resistor r1 should be placed close to the switching node, to prevent noise from coupling into sensitive small-signal nodes. the capacitor c1 should be placed close to the ic pins. because of possible pcb noise in the current sensing loop, the ac current sensing ripple of ?v sense = ?i l ? r sense also needs to be checked in the design to get a good signal-to- noise ratio. in general, for a reasonably good pcb layout, a 10mv ?v sense voltage is recommended as a conservative number to start with, either for r sense or dcr sensing applications, for duty cycles less than 40%. for previous generation current mode controllers, the maximum sense voltage was high enough (e.g., 75mv for the ltc1628 / ltc3728 family) that the voltage drop across the parasitic inductance of the sense resistor represented a relatively small error. for todays highest current density solutions, however, the value of the sense resistor can be less than 1m? and the peak sense voltage can be as low as 20mv. in addition, inductor ripple currents greater than 50% with operation up to 1mhz are becoming more common. under these conditions the voltage drop across the sense resistors parasitic inductance is no longer neg- ligible. a typical sensing circuit using a discrete resistor is shown in figure 2a. in previous generations of controllers, a small rc flter placed near the ic was commonly used to reduce the effects of capacitive and inductive noise coupled inthe sense traces on the pcb. a typical flter consists of two series 10? resistors connected to a parallel 1000pf capacitor, resulting in a time constant of 20ns. this same rc flter, with minor modifcations, can be used to extract the resistive component of the current sense signal in the presence of parasitic inductance. for example, figure 3 illustrates the voltage waveform across a 2m? sense resistor with a 2010 footprint for the 1.2v/15a converter operating at 100% load. the waveform is the superposition of a purely resistive component and a purely inductive component. it was measured using two scope probes and waveform math to obtain a differential measurement. based on additional measurements of the inductor ripple current and the on-time and off-time of the top switch, the value of the parasitic inductance was determined to be 0.5nh using the equation: esl v i t t t t esl step l on off on off = ? + ( ) ? if the rc time constant is chosen to be close to the parasitic inductance divided by the sense resistor (l/r), a pplica t ions i n f or m a t ion figure 1. sense lines placement with sense resistor c out to sense filter, next to the controller r sense 3855 f01 low value resistors current sensing a typical sensing circuit using a discrete resistor is shown in figure 2a. r sense is chosen based on the required output current. the current comparator has a maximum threshold v sense(max) determined by the i lim setting. the input common mode range of the current comparator is 0v to 12.5v. the current comparator threshold sets the peak of the inductor current, yielding a maximum average output current i max equal to the peak value less half the peak-to- peak ripple current, ?i l . to calculate the sense resistor value, use the equation: r sense = v sense(max) i (max) + ? i l 2
LTC3855 3855f the above generally applies to high density/high current applications where i (max) >10a and low values of induc- tors are used. for applications where i (max) <10a, set r f to 10 ohms and c f to 1000pf. this will provide a good starting point. the flter components need to be placed close to the ic. the positive and negative sense traces need to be routed as a differential pair and kelvin connected to the sense resistor. inductor dcr sensing for applications requiring the highest possible effciency at high load currents, the LTC3855 is capable of sensing the voltage drop across the inductor dcr, as shown in figure 2b. the dcr of the inductor represents the small amount of dc winding resistance of the copper, which can be less than 1m? for todays low value, high current inductors. in a high current application requiring such an inductor, conduction loss through a sense resistor would cost sev- eral points of effciency compared to dcr sensing. if the external r1 || r2 ? c1 time constant is chosen to be exactly equal to the l/dcr time constant, the voltage drop across the external capacitor is equal to the drop across the inductor dcr multiplied by r2/(r1 + r2). r2 scales the voltage across the sense terminals for applications where the dcr is greater than the target sense resistor value. to properly dimension the external flter components, the dcr of the inductor must be known. it can be measured using a good rlc meter, but the dcr tolerance is not a pplica t ions i n f or m a t ion figure 2. two different methods of sensing current (2a) using a resistor to sense current (2b) using the inductor dcr to sense current v in v in intv cc boost tg sw bg pgnd filter components placed near sense pins sense + sense ? sgnd LTC3855 v out 3855 f02a c f ? 2 rf esl/r s pole-zero cancellation sense resistor plus parasitic inductance r s esl c f r f r f v in v in intv cc itemp boost tg sw bg pgnd *place c1 near sense + , sense ? pins **place r1 next to inductor inductor dcrl sense + sense ? sgnd LTC3855 optional temp comp network v out 3855 f02b r1** r2c1* r p r ntc r s r1 || r2 c1 = l dcr r sense(eq) = dcr r2 r1 + r2 figure 3. voltage waveform measured directly across the sense resistor. figure 4. voltage waveform measured after the sense resistor filter. c f = 1000pf, r f = 100?. 500ns/div v sense 20mv/div 3855 f03 v esl(step) 500ns/div v sense 20mv/div 3855 f04 the resulting waveform looks resistive again, as shown in figure 4. for applications using low maximum sense voltages, check the sense resistor manufacturers data sheet for information about parasitic inductance. in the absence of data, measure the voltage drop directly across the sense resistor to extract the magnitude of the esl step and use the equation above to determine the esl. however, do not over-flter. keep the rc time constant less than or equal to the inductor time constant to maintain a high enough ripple voltage on v rsense .
LTC3855 3855f a pplica t ions i n f or m a t ion always the same and varies with temperature; consult the manufacturers datasheets for detailed information. using the inductor ripple current value from the inductor value calculation section, the target sense resistor value is: r sense(equiv) = v sense(max) i (max) + ? i l 2 to ensure that the application will deliver full load current over the full operating temperature range, choose the minimum value for the maximum current sense threshold (v sense(max) ) in the electrical characteristics table (25mv, 45mv, or 68mv, depending on the state of the i lim pin). next, determine the dcr of the inductor. where provided, use the manufacturers maximum value, usually given at 20c. increase this value to account for the temperature coeffcient of resistance, which is approximately 0.4%/c or use LTC3855 dcr temperature compensation function. a conservative value for t l(max) is 100c. to scale the maximum inductor dcr to the desired sense resistor value, use the divider ratio: r d = r sense(equiv) dcr (max) at t l(max) c1 is usually selected to be in the range of 0.047f to 0.47f. this forces r1 || r2 to around 2k?, reducing error that might have been caused by the sense pins 1a current. t l(max) is the maximum inductor temperature. the equivalent resistance r1 || r2 is scaled to the room temperature inductance and maximum dcr: r1||r2 = l (dcr at 20 c) ? c1 the sense resistor values are: r1 = r1|| r2 r d ; r2 = r1 ? r d 1 ? r d the maximum power loss in r1 is related to duty cycle, and will occur in continuous mode at the maximum input voltage: p loss r1 = v in(max) ? v out ( ) ? v out r1 ensure that r1 has a power rating higher than this value. if high effciency is necessary at light loads, consider this power loss when deciding whether to use dcr sensing or sense resistors. light load power loss can be modestly higher with a dcr network than with a sense resistor, due to the extra switching losses incurred through r1. however, dcr sensing eliminates a sense resistor, reduces conduc- tion losses and provides higher effciency at heavy loads. peak effciency is about the same with either method. to maintain a good signal to noise ratio for the current sense signal, use a minimum ?v sense of 10mv for duty cycles less than 40%. for a dcr sensing application, the actual ripple voltage will be determined by the equation: ? = ? v v v r c v v f sense in out out in osc 1 1? ? ntc compensated dcr sensing for dcr sensing applications where a more accurate current limit is required, a network consisting of an ntc thermistor placed from the itemp pin to ground will provide correction of the current limit over temperature. figure 2b shows this network. resistors r s and r p will linearize the impedance the itemp pin sees. to implement ntc compensated dcr sensing, design the dcr sense flter network per the same procedure mentioned in the previous selection, except calculate the divider components using the room temperature value of the dcr. for a single output rail operating from one phase: 1. set the itemp pin resistance to 50k at 25c. with 10a fowing out of the itemp pin, the voltage on the itemp pin will be 0.5v at room temperature. current limit correction will occur for inductor temperatures greater than 25c. 2. calculate the itemp pin resistance and the maximum inductor temperature which is typically 100c. use the following equations:
LTC3855 3855f r v a itemp c itemp c 100 100 10 = v v i dcr max r r r itemp c max 100 0 5 1 3 2 1 2 = ? ? ? ? + ? . . ( ) ( 1100 25 0 4 100 ? ? c c v sense max ) . ( ) calculate the values for r p and r s . a simple method is to graph the following r s versus r p equations with r s on the y-axis and r p on the x-axis. r s = r itemp25c C r ntc25c || r p r s = r itemp100c C r ntc100c || r p next, fnd the value of r p that satisfes both equations which will be the point where the curves intersect. once r p is known, solve for r s . the resistance of the ntc thermistor can be obtained from the vendors data sheet either in the form of graphs, tabulated data, or formulas. the approximate value for the ntc thermistor for a given temperature can be calculated from the following equation: r r b t t o o = ? ? + ? + ? ? ? ? ? ? ? ? ? ? ? ? exp 1 273 1 273 where r = resistance at temperature t, which is in degrees c r o = resistance at temperature t o , typically 25c b = b-constant of the thermistor figure 5 shows a typical resistance curve for a 100k therm- istor and the itemp pin network over temperature. starting values for the ntc compensation network are: ? ntc r o = 100k ? r s = 20k ? r p = 50k but, the fnal values should be calculated using the above equations and checked at 25c and 100c. after determining the components for the temperature compensation network, check the results by plotting i max versus inductor temperature using the following equations: i v v dcr max max sensemax adj sense = ? ( ) ( ) ? 2 at 25 cc t c l max ? + ? ( ) ? ? ? ? ? ? ? 1 25 0 4 100 ( ) . where v v v v a sensemax adj sense max itemp ( ) ( ) . . = ? ? ? 1 8 1 3 v itemp = 10a ? (r s + r p || r ntc ) use typical values for v sense(max) . subtracting constant a will provide a minimum value for v sense(max) . these values are summarized in table 2. table 2. i lim gnd float intv cc v sense(max) typ 30mv 50mv 75mv a 5mv 5mv 7mv the resulting current limit should be greater than or equal to i max for inductor temperatures between 25c and 100c. typical values for the ntc compensation network are: ? ntc r o = 100k, b-constant = 3000 to 4000 ? r s 20k ? r p 50k generating the i max versus inductor temperature curve plot frst using the above values as a starting point and then adjusting the r s and r p values as necessary is another approach. figure 6 shows a typical curve of i max versus inductor temperature. for polyphase applications, tie the itemp pins together and calculate for an itemp pin cur- rent of 10a ? #phases. the same thermistor network can be used to correct for temperatures less than 25c. but make sure v itemp is a pplica t ions i n f or m a t ion
LTC3855 0 3855f greater than 0.2v for duty cycles of 25% or more, oth- erwise temperature correction may not occur at elevated ambients. for the most accurate temperature detection, place the thermistors next to the inductors as shown in figure 7. take care to keep the itemp pins away from the switch nodes. slope compensation and inductor peak current slope compensation provides stability in constant- frequency architectures by preventing subharmonic oscil- lations at high duty cycles. it is accomplished internally by adding a compensating ramp to the inductor current signal at duty cycles in excess of 40%. normally, this results in a reduction of maximum inductor peak current for duty cycles > 40%. however, the LTC3855 uses a scheme that counteracts this compensating ramp, which allows the maximum inductor peak current to remain unaffected throughout all duty cycles. inductor value calculation given the desired input and output voltages, the inductor value and operating frequency f osc directly determine the inductors peak-to-peak ripple current: i ripple = v out v in v in ? v out f osc ? l ? ? ? ? ? ? lower ripple current reduces core losses in the inductor, esr losses in the output capacitors, and output voltage ripple. thus, highest effciency operation is obtained at low frequency with a small ripple current. achieving this, however, requires a large inductor. figure 7. thermistor locations. place thermistor next to inductor(s) for accurate sensing of the inductor temperature, but keep the itemp pins away from the switch nodes and gate drive traces figure 5. resistance versus temperature for itemp pin network and the 100k ntc figure 6. worst case i max versus inductor temperature curve with and without ntc temperature compensation a pplica t ions i n f or m a t ion (7a) dual output dual phase dcr sensing application (7b) single output dual phase dcr sensing application 10000 1000 100 10 1 inductor temperature (c) ?40 resistance (k) 0 40 ?20 20 80 3855 f05 120 60 100 ritmp r s = 20k r p = 43.2k 100k ntc thermistor resistance r o = 100k, t o = 25c b = 4334 for 25c/100c 25 20 15 10 5 0 inductor temperature (c) ?40 i max (a) 0 40 ?20 20 80 3855 f06 120 60 100 r s = 20k r p = 43.2k ntc thermistor: r o = 100k t o = 25c b = 4334 corrected i max uncorrected i max nominal i max connect to itemp1 network connect to itemp2 network r ntc2 gnd r ntc1 gnd 3855 f07a v out1 sw1 l1 v out2 sw2 l2 r ntc 3855 f07b v out sw1 l1 sw2 l2
LTC3855 3855f a pplica t ions i n f or m a t ion a reasonable starting point is to choose a ripple current that is about 40% of i out(max) for a duty cycle less than 40%. note that the largest ripple current occurs at the highest input voltage. to guarantee that ripple current does not exceed a specifed maximum, the inductor should be chosen according to: l v in ? v out f osc ?i ripple ? v out v in for duty cycles greater than 40%, the 10mv current sense ripple voltage requirement is relaxed because the slope compensation signal aids the signal-to-noise ratio and because a lower limit is placed on the inductor value to avoid subharmonic oscillations. to ensure stability for duty cycles up to the maximum of 95%, use the following equation to fnd the minimum inductance. l v f i min out sw load max > ? ? . ( ) 1 4 where l min is in units of h f sw is in units of mhz inductor core selection once the inductance value is determined, the type of in- ductor must be selected. core loss is independent of core size for a fxed inductor value, but it is very dependent on inductance selected. as inductance increases, core losses go down. unfortunately, increased inductance requires more turns of wire and therefore copper losses will increase. ferrite designs have very low core loss and are preferred at high switching frequencies, so design goals can con- centrate on copper loss and preventing saturation. ferrite core material saturates hard, which means that induc- tance collapses abruptly when the peak design current is exceeded. this results in an abrupt increase in inductor ripple current and consequent output voltage ripple. do not allow the core to saturate! power mosfet and schottky diode (optional) selection two external power mosfets must be selected for each controller in the LTC3855: one n-channel mosfet for the top (main) switch, and one n-channel mosfet for the bottom (synchronous) switch. the peak-to-peak drive levels are set by the intv cc voltage. this voltage is typically 5v during start-up (see extv cc pin connection). consequently, logic-level threshold mosfets must be used in most applications. the only exception is if low input voltage is expected (v in < 5v); then, sub-logic level threshold mosfets (v gs(th) < 3v) should be used. pay close attention to the bv dss specifcation for the mosfets as well; most of the logic level mosfets are limited to 30v or less. selection criteria for the power mosfets include the on-resistance r ds(on) , miller capacitance c miller , input voltage and maximum output current. miller capacitance, c miller , can be approximated from the gate charge curve usually provided on the mosfet manufacturers data sheet. c miller is equal to the increase in gate charge along the horizontal axis while the curve is approximately fat divided by the specifed change in v ds . this result is then multiplied by the ratio of the application applied v ds to the gate charge curve specifed v ds . when the ic is operating in continuous mode the duty cycles for the top and bottom mosfets are given by: main switch duty cycle = v out v in synchronous switch duty cycle = v in ? v out v in
LTC3855 3855f a pplica t ions i n f or m a t ion the mosfet power dissipations at maximum output current are given by: p v v i r v i main out in max ds on in max = ( ) + ( ) + ( ) 2 2 1 d ( ) 22 1 1 ? ? ? ? ? ? ( )( ) + r c v v v dr miller intvcc th min ? ? ( ) tth min osc sync in out in max f p v v v i ( ) ? ? ? ? ? ? ? ? ? ? = ( )) + ( ) 2 1 d r ds on( ) where d is the temperature dependency of r ds(on) and r dr (approximately 2?) is the effective driver resistance at the mosfets miller threshold voltage. v th(min) is the typical mosfet minimum threshold voltage. both mosfets have i 2 r losses while the topside n-channel equation includes an additional term for transition losses, which are highest at high input voltages. for v in < 20v the high current effciency generally improves with larger mosfets, while for v in > 20v the transition losses rapidly increase to the point that the use of a higher r ds(on) device with lower c miller actually provides higher effciency. the synchronous mosfet losses are greatest at high input voltage when the top switch duty factor is low or during a short-circuit when the synchronous switch is on close to 100% of the period. the term (1 + d ) is generally given for a mosfet in the form of a normalized r ds(on) vs temperature curve, but d = 0.005/c can be used as an approximation for low voltage mosfets. the optional schottky diodes conduct during the dead time between the conduction of the two power mosfets. these prevent the body diodes of the bottom mosfets from turn- ing on, storing charge during the dead time and requiring a reverse recovery period that could cost as much as 3% in effciency at high v in . a 1a to 3a schottky is generally a good compromise for both regions of operation due to the relatively small average current. larger diodes result in additional transition losses due to their larger junction capacitance. a schottky diode in parallel with the bottom fet may also provide a modest improvement in burst mode effciency. soft-start and tracking the LTC3855 has the ability to either soft-start by itself with a capacitor or track the output of another channel or external supply. when one particular channel is confgured to soft-start by itself, a capacitor should be connected to its tk/ss pin. this channel is in the shutdown state if its run pin voltage is below 1.2v. its tk/ss pin is actively pulled to ground in this shutdown state. once the run pin voltage is above 1.2v, the channel pow- ers up. a soft-start current of 1.2a then starts to charge its soft-start capacitor. note that soft-start or tracking is achieved not by limiting the maximum output current of the controller but by controlling the output ramp voltage according to the ramp rate on the tk/ss pin. current foldback is disabled during this phase to ensure smooth soft-start or tracking. the soft-start or tracking range is defned to be the voltage range from 0v to 0.6v on the tk/ss pin. the total soft-start time can be calculated as: t softstart = 0.6 ? c ss 1.2 a regardless of the mode selected by the mode/pllin pin, the regulator will always start in pulse-skipping mode up to tk/ss = 0.5v. between tk/ss = 0.5v and 0.54v, it will operate in forced continuous mode and revert to the selected mode once tk/ss > 0.54v. the output ripple is minimized during the 40mv forced continuous mode window ensuring a clean pgood signal. when the channel is confgured to track another supply, the feedback voltage of the other supply is duplicated by a resistor divider and applied to the tk/ss pin. therefore, the voltage ramp rate on this pin is determined by the ramp rate of the other supplys voltage. note that the small soft-start capacitor charging current is always fowing,
LTC3855 3855f a pplica t ions i n f or m a t ion producing a small offset error. to minimize this error, select the tracking resistive divider value to be small enough to make this error negligible. in order to track down another channel or supply after the soft-start phase expires, the LTC3855 is forced into continuous mode of operation as soon as v fb is below the undervoltage threshold of 0.54v regardless of the setting on the mode/pllin pin. however, the LTC3855 should always be set in force continuous mode tracking down when there is no load. after tk/ss drops below 0.1v, its channel will operate in discontinuous mode. output voltage tracking the LTC3855 allows the user to program how its output ramps up and down by means of the tk/ss pins. through these pins, the output can be set up to either coincidentally or ratiometrically track another supplys output, as shown in figure 8. in the following discussions, v out1 refers to the LTC3855s output 1 as a master channel and v out2 refers to the LTC3855s output 2 as a slave channel. in practice, though, either phase can be used as the master. to implement the coincident tracking in figure 8a, con- nect an additional resistive divider to v out1 and connect its midpoint to the tk/ss pin of the slave channel. the ratio of this divider should be the same as that of the slave channels feedback divider shown in figure 9a. in this tracking mode, v out1 must be set higher than v out2 . to implement the ratiometric tracking in figure 9b, the ratio of the v out2 divider should be exactly the same as the master channels feedback divider shown in figure 9b. by select- ing different resistors, the LTC3855 can achieve different modes of tracking including the two in figure 8. so which mode should be programmed? while either mode in figure 8 satisfes most practical applications, some tradeoffs exist. the ratiometric mode saves a pair of resistors, but the coincident mode offers better output regulation. when the master channels output experiences dynamic excursion (under load transient, for example), the slave channel output will be affected as well. for better output regulation, use the coincident tracking mode instead of ratiometric. figure 8. two different modes of output voltage tracking figure 9. setup for coincident and ratiometric tracking time (8a) coincident tracking v out1 v out2 output voltage 3855 f08a v out1 v out2 time 3855 f08b (8b) ratiometric tracking output voltage r3 r1 r4 r2 r3 v out2 r4 (9a) coincident tracking setup to v fb1 pin to tk/ss2 pin to v fb2 pin v out1 r1 r2 r3 v out2 r4 3855 f09 (9b) ratiometric tracking setup to v fb1 pin to tk/ss2 pin to v fb2 pin v out1
LTC3855 3855f a pplica t ions i n f or m a t ion intv cc regulators and extv cc the LTC3855 features a true pmos ldo that supplies power to intv cc from the v in supply. intv cc powers the gate drivers and much of the LTC3855s internal circuitry. the linear regulator regulates the voltage at the intv cc pin to 5v when v in is greater than 5.5v. extv cc connects to intv cc through a p-channel mosfet and can supply the needed power when its voltage is higher than 4.7v. each of these can supply a peak current of 100ma and must be bypassed to ground with a minimum of 4.7f ceramic capacitor or low esr electrolytic capacitor. no matter what type of bulk capacitor is used, an additional 0.1f ceramic capacitor placed directly adjacent to the intv cc and pgnd pins is highly recommended. good bypassing is needed to supply the high transient currents required by the mosfet gate drivers and to prevent interaction between the channels. high input voltage applications in which large mosfets are being driven at high frequencies may cause the maxi- mum junction temperature rating for the LTC3855 to be exceeded. the intv cc current, which is dominated by the gate charge current, may be supplied by either the 5v linear regulator or extv cc . when the voltage on the extv cc pin is less than 4.7v, the linear regulator is enabled. power dissipation for the ic in this case is highest and is equal to v in ? i intvcc . the gate charge current is dependent on operating frequency as discussed in the effciency considerations section. the junction temperature can be estimated by using the equations given in note 3 of the electrical characteristics. for example, the LTC3855 intv cc current is limited to less than 44ma from a 38v supply in the uj package and not using the extv cc supply: t j = 70c + (44ma)(38v)(33c/w) = 125c to prevent the maximum junction temperature from being exceeded, the input supply current must be checked while operating in continuous conduction mode (mode/pllin = sgnd) at maximum v in . when the voltage applied to ext- v cc rises above 4.7v, the intv cc linear regulator is turned off and the extv cc is connected to the intv cc . the extv cc remains on as long as the voltage applied to extv cc remains above 4.5v. using the extv cc allows the mosfet driver and control power to be derived from one of the LTC3855s switching regulator outputs during normal operation and from the intv cc when the output is out of regulation (e.g., start-up, short-circuit). if more current is required through the extv cc than is specifed, an external schottky diode can be added between the extv cc and intv cc pins. do not apply more than 6v to the extv cc pin and make sure that extv cc < v in . signifcant effciency and thermal gains can be realized by powering intv cc from the output, since the v in current resulting from the driver and control currents will be scaled by a factor of (duty cycle)/(switcher effciency). tying the extv cc pin to a 5v supply reduces the junction temperature in the previous example from 125c to: t j = 70c + (44ma)(5v)(33c/w) = 77c however, for 3.3v and other low voltage outputs, addi- tional circuitry is required to derive intv cc power from the output. the following list summarizes the four possible connec- tions for extv cc : 1. extv cc left open (or grounded). this will cause intv cc to be powered from the internal 5v regulator resulting in an effciency penalty of up to 10% at high input voltages. 2. extv cc connected directly to v out . this is the normal connection for a 5v regulator and provides the highest effciency. 3. extv cc connected to an external supply. if a 5v external supply is available, it may be used to power extv cc providing it is compatible with the mosfet gate drive requirements. 4. extv cc connected to an output-derived boost net- work. for 3.3v and other low voltage regulators, effciency gains can still be realized by connecting extv cc to an output-derived voltage that has been boosted to greater than 4.7v. for applications where the main input power is below 5v, tie the v in and intv cc pins together and tie the combined pins to the 5v input with a 1? or 2.2? resistor as shown in figure 10 to minimize the voltage drop caused by the gate charge current. this will override the intv cc linear regulator and will prevent intv cc from dropping too low
LTC3855 3855f a pplica t ions i n f or m a t ion due to the dropout voltage. make sure the intv cc voltage is at or exceeds the r ds(on) test voltage for the mosfet which is typically 4.5v for logic level devices. another way to detect an undervoltage condition is to monitor the v in supply. because the run pins have a precision turn-on reference of 1.2v, one can use a resistor divider to v in to turn on the ic when v in is high enough. an extra 4.5a of current fows out of the run pin once the run pin voltage passes 1.2v. one can program the hysteresis of the run comparator by adjusting the values of the resistive divider. for accurate v in undervoltage detection, v in needs to be higher than 4.5v. c in and c out selection the selection of c in is simplifed by the 2-phase architec- ture and its impact on the worst-case rms current drawn through the input network (battery/fuse/capacitor). it can be shown that the worst-case capacitor rms current occurs when only one controller is operating. the controller with the highest (v out )(i out ) product needs to be used in the formula below to determine the maximum rms capacitor current requirement. increasing the output current drawn from the other controller will actually decrease the input rms ripple current from its maximum value. the out-of- phase technique typically reduces the input capacitors rms ripple current by a factor of 30% to 70% when compared to a single phase power supply solution. in continuous mode, the source current of the top mosfet is a square wave of duty cycle (v out )/(v in ). to prevent large voltage transients, a low esr capacitor sized for the maximum rms current of one channel must be used. the maximum rms capacitor current is given by: c in required i rms i max v in v out ( ) v in ? v out ( ) ? ? ? ? 1/ 2 this formula has a maximum at v in = 2v out , where i rms = i out /2. this simple worst-case condition is commonly used for design because even signifcant deviations do not of- fer much relief. note that capacitor manufacturers ripple current ratings are often based on only 2000 hours of life. this makes it advisable to further derate the capacitor, or to choose a capacitor rated at a higher temperature than required. several capacitors may be paralleled to meet size or height requirements in the design. due to the high operating frequency of the LTC3855, ceramic capacitors figure 10. setup for a 5v input intv cc LTC3855 r vin 1 c in 3855 f07 4.7f 5v cintv cc + v in topside mosfet driver supply (c b , db) external bootstrap capacitors c b connected to the boost pins supply the gate drive voltages for the topside mosfets. capacitor c b in the functional diagram is charged though external diode db from intv cc when the sw pin is low. when one of the topside mosfets is to be turned on, the driver places the c b voltage across the gate source of the desired mosfet. this enhances the mosfet and turns on the topside switch. the switch node voltage, sw, rises to v in and the boost pin follows. with the topside mosfet on, the boost voltage is above the input supply: v boost = v in + v intvcc . the value of the boost capacitor c b needs to be 100 times that of the total input capa- citance of the topside mosfet(s). the reverse break- down of the external schottky diode must be greater than v in(max) . when adjusting the gate drive level, the fnal arbiter is the total input current for the regulator. if a change is made and the input current decreases, then the effciency has improved. if there is no change in input current, then there is no change in effciency. undervoltage lockout the LTC3855 has two functions that help protect the controller in case of undervoltage conditions. a precision uvlo comparator constantly monitors the intv cc voltage to ensure that an adequate gate-drive voltage is present. it locks out the switching action when intv cc is below 3.2v. to prevent oscillation when there is a disturbance on the intv cc , the uvlo comparator has 600mv of precision hysteresis.
LTC3855 3855f can also be used for c in . always consult the manufacturer if there is any question. the beneft of the LTC3855 2-phase operation can be cal- culated by using the equation above for the higher power controller and then calculating the loss that would have resulted if both controller channels switched on at the same time. the total rms power lost is lower when both control- lers are operating due to the reduced overlap of current pulses required through the input capacitors esr. this is why the input capacitors requirement calculated above for the worst-case controller is adequate for the dual controller design. also, the input protection fuse resistance, battery resistance, and pc board trace resistance losses are also reduced due to the reduced peak currents in a 2-phase system. the overall beneft of a multiphase design will only be fully realized when the source impedance of the power supply/battery is included in the effciency testing. the sources of the top mosfets should be placed within 1cm of each other and share a common c in (s). separating the sources and c in may produce undesirable voltage and current resonances at v in . a small (0.1f to 1f) bypass capacitor between the chip v in pin and ground, placed close to the LTC3855, is also suggested. a 2.2? to 10? resistor placed between c in (c1) and the v in pin provides further isolation between the two channels. the selection of c out is driven by the effective series resistance (esr). typically, once the esr requirement is satisfed, the capacitance is adequate for fltering. the output ripple (?v out ) is approximated by: ? v out i ripple esr + 1 8fc out ? ? ? ? ? ? where f is the operating frequency, c out is the output capacitance and i ripple is the ripple current in the induc- tor. the output ripple is highest at maximum input voltage since i ripple increases with input voltage. setting output voltage the LTC3855 output voltages are each set by an external feedback resistive divider carefully placed across the output, as shown in figure 11. the regulated output voltage is determined by: v out = 0.6v ? 1 + r b r a ? ? ? ? ? ? to improve the frequency response, a feed-forward ca- pacitor, c ff , may be used. great care should be taken to route the v fb line away from noise sources, such as the inductor or the sw line. a pplica t ions i n f or m a t ion fault conditions: current limit and current foldback the LTC3855 includes current foldback to help limit load current when the output is shorted to ground. if the out- put falls below 50% of its nominal output level, then the maximum sense voltage is progressively lowered from its maximum programmed value to one-third of the maximum value. foldback current limiting is disabled during the soft-start or tracking up. under short-circuit conditions with very low duty cycles, the LTC3855 will begin cycle skipping in order to limit the short-circuit current. in this situation the bottom mosfet will be dissipating most of the power but less than in normal operation. the short- circuit ripple current is determined by the minimum on- time t on(min) of the LTC3855 ( 90ns), the input voltage and inductor value: ? i l(sc) = t on(min) ? v in l the resulting short-circuit current is: i sc = 1/3 v sense(max) r sense ? 1 2 ? i l(sc) figure 11. setting output voltage 1/2 LTC3855 v fb v out r b c ff r a 3855 f11
LTC3855 3855f phase-locked loop and frequency synchronization the LTC3855 has a phase-locked loop (pll) comprised of an internal voltage-controlled oscillator (v co ) and a phase detector. this allows the turn-on of the top mosfet of controller 1 to be locked to the rising edge of an external clock signal applied to the mode/pllin pin. the turn-on of controller 2s top mosfet is thus 180 degrees out- of-phase with the external clock. the phase detector is an edge sensitive digital type that provides zero degrees phase shift between the external and internal oscillators. this type of phase detector does not exhibit false lock to harmonics of the external clock. the output of the phase detector is a pair of complementary current sources that charge or discharge the internal flter network. there is a precision 10a of current fowing out of freq pin. this allows the user to use a single resistor to sgnd to set the switching frequency when no external clock is applied to the mode/pllin pin. the internal switch between freq pin and the integrated pll flter network is on, allowing the flter network to be pre-charged to the same voltage potential as the freq pin. the relationship between the voltage on the freq pin and the operating frequency is shown in figure 12 and specifed in the elec- trical characteristic table. if an external clock is detected on the mode/pllin pin, the internal switch mentioned above will turn off and isolate the infuence of freq pin. note that the LTC3855 can only be synchronized to an external clock whose frequency is within range of the LTC3855s internal v co . this is guaranteed to be between 250khz and 770khz. a simplifed block diagram is shown in figure 13. if the external clock frequency is greater than the internal oscillators frequency, f osc , then current is sourced continu- ously from the phase detector output, pulling up the flter network. when the external clock frequency is less than f osc , current is sunk continuously, pulling down the flter network. if the external and internal frequencies are the same but exhibit a phase difference, the current sources turn on for an amount of time corresponding to the phase difference. the voltage on the flter network is adjusted until the phase and frequency of the internal and external oscillators are identical. at the stable operating point, the phase detector output is high impedance and the flter capacitor holds the voltage. typically, the external clock (on mode/pllin pin) input high threshold is 1.6v, while the input low threshold is 1v. it is not recommended to apply the external clock when ic is in shutdown. minimum on-time considerations minimum on-time t on(min) is the smallest time duration that the LTC3855 is capable of turning on the top mosfet. it is determined by internal timing delays and the gate charge required to turn on the top mosfet. low duty cycle applications may approach this minimum on-time limit and care should be taken to ensure that t on(min) < v out v in (f) a pplica t ions i n f or m a t ion figure 12. relationship between oscillator frequency and voltage at the freq pin freq pin voltage (v) 0 frequency (khz) 0.5 1 1.5 2 3855 f12 2.5 0 100 300 400 500 900 800 700 200 600 figure 13. phase-locked loop block diagram digital phase/ frequency detector sync vco 2.4v 5v 10a r set 3855 f13 freq external oscillator mode/ pllin
LTC3855 3855f if the duty cycle falls below what can be accommodated by the minimum on-time, the controller will begin to skip cycles. the output voltage will continue to be regulated, but the ripple voltage and current will increase. the minimum on-time for the LTC3855 is approximately 90ns, with reasonably good pcb layout, minimum 30% inductor current ripple and at least 10mv C 15mv ripple on the current sense signal. the minimum on-time can be affected by pcb switching noise in the voltage and current loop. as the peak sense voltage decreases the minimum on-time gradually increases to 130ns. this is of particular concern in forced continuous applications with low ripple current at light loads. if the duty cycle drops below the minimum on-time limit in this situation, a signifcant amount of cycle skipping can occur with correspondingly larger current and voltage ripple. effciency considerations the percent effciency of a switching regulator is equal to the output power divided by the input power times 100%. it is often useful to analyze individual losses to determine what is limiting the effciency and which change would produce the most improvement. percent effciency can be expressed as: %effciency = 100% C (l1 + l2 + l3 + ...) where l1, l2, etc. are the individual losses as a percent- age of input power. although all dissipative elements in the circuit produce losses, four main sources usually account for most of the losses in LTC3855 circuits: 1) ic v in current, 2) intv cc regulator current, 3) i 2 r losses, 4) topside mosfet transition losses. 1. the v in current is the dc supply current given in the electrical characteristics table, which excludes mosfet driver and control currents. v in current typi- cally results in a small (<0.1%) loss. 2. intv cc current is the sum of the mosfet driver and control currents. the mosfet driver current results from switching the gate capacitance of the power mosfets. each time a mosfet gate is switched from low to high to low again, a packet of charge dq moves from intv cc to ground. the resulting dq/dt is a cur- rent out of intv cc that is typically much larger than the control circuit current. in continuous mode, i gatechg = f(q t + q b ), where q t and q b are the gate charges of the topside and bottom side mosfets. supplying intv cc power through extv cc from an out- put-derived source will scale the v in current required for the driver and control circuits by a factor of (duty cycle)/(effciency). for example, in a 20v to 5v applica- tion, 10ma of intv cc current results in approximately 2.5ma of v in current. this reduces the mid-current loss from 10% or more (if the driver was powered directly from v in ) to only a few percent. 3. i 2 r losses are predicted from the dc resistances of the fuse (if used), mosfet, inductor, current sense resistor. in continuous mode, the average output current fows through l and r sense , but is chopped between the topside mosfet and the synchronous mosfet. if the two mosfets have approximately the same r ds(on) , then the resistance of one mosfet can simply be summed with the resistances of l and r sense to ob- tain i 2 r losses. for example, if each r ds(on) = 10m?, r l = 10m?, r sense = 5m?, then the total resistance is 25m?. this results in losses ranging from 2% to 8% as the output current increases from 3a to 15a for a 5v output, or a 3% to 12% loss for a 3.3v output. effciency varies as the inverse square of v out for the same external components and output power level. the combined effects of increasingly lower output voltages and higher currents required by high performance digital systems is not doubling but quadrupling the importance of loss terms in the switching regulator system! 4. t ransition losses apply only to the topside mosfet(s), and become signifcant only when operating at high input voltages (typically 15v or greater). transition losses can be estimated from: transition loss = (1.7) v in 2 i o(max) c rss f other hidden losses such as copper trace and internal battery resistances can account for an additional 5% to 10% effciency degradation in portable systems. it is very important to include these system level losses during the design phase. the internal battery and fuse resistance a pplica t ions i n f or m a t ion
LTC3855 3855f losses can be minimized by making sure that c in has adequate charge storage and very low esr at the switch- in g frequency. a 25w supply will typically require a minimum of 20f to 40f of capacitance having a maximum of 20m? to 50m? of esr. the LTC3855 2-phase architecture typically halves this input capacitance requirement over competing solutions. other losses including schottky conduction losses during dead time and inductor core losses generally account for less than 2% total additional loss. modest improvements in burst mode effciency may be realized by using a smaller inductor value, a lower switch- ing frequency or for dcr sensing applications, making the dcr flters time constant smaller than the l/dcr time constant for the inductor. a small schottky diode with a current rating equal to about 20% of the maximum load current or less may yield minor improvements, too. checking transient response the regulator loop response can be checked by looking at the load current transient response. switching regulators take several cycles to respond to a step in dc (resistive) load current. when a load step occurs, v out shifts by an amount equal to ?i load (esr), where esr is the effective series resistance of c out . ?i load also begins to charge or discharge c out generating the feedback error signal that forces the regulator to adapt to the current change and return v out to its steady-state value. during this recovery time v out can be monitored for excessive overshoot or ringing, which would indicate a stability problem. the availability of the i th pin not only allows optimization of control loop behavior but also provides a dc coupled and ac fltered closed loop response test point. the dc step, rise time and settling at this test point truly refects the closed loop response. assuming a predominantly second order system, phase margin and/or damping factor can be estimated using the percentage of overshoot seen at this pin. the bandwidth can also be estimated by examining the rise time at the pin. the i th external components shown in the typical application circuit will provide an adequate starting point for most applications. the i th series r c -c c flter sets the dominant pole-zero loop compensation. the values can be modifed slightly (from 0.5 to 2 times their suggested values) to optimize transient response once the fnal pc layout is done and the particular output capacitor type and value have been determined. the output capacitors need to be selected because the various types and values determine the loop gain and phase. an output current pulse of 20% to 80% of full-load current having a rise time of 1s to 10s will produce output voltage and i th pin waveforms that will give a sense of the overall loop stability without break- ing the feedback loop. placing a power mosfet directly across the output capacitor and driving the gate with an appropriate signal generator is a practical way to produce a realistic load step condition. the initial output voltage step resulting from the step change in output current may not be within the bandwidth of the feedback loop, so this signal cannot be used to determine phase margin. this is why it is better to look at the i th pin signal which is in the feedback loop and is the fltered and compensated control loop response. the gain of the loop will be in- creased by increasing r c and the bandwidth of the loop will be increased by decreasing c c . if r c is increased by the same factor that c c is decreased, the zero frequency will be kept the same, thereby keeping the phase shift the same in the most critical frequency range of the feedback loop. the output voltage settling behavior is related to the stability of the closed-loop system and will demonstrate the actual overall supply performance. a second, more severe transient is caused by switching in loads with large (>1f) supply bypass capacitors. the discharged bypass capacitors are effectively put in parallel with c out , causing a rapid drop in v out . no regulator can alter its delivery of current quickly enough to prevent this sudden step change in output voltage if the load switch resistance is low and it is driven quickly. if the ratio of c load to c out is greater than 1:50, the switch rise time should be controlled so that the load rise time is limited to approximately 25 ? c load . thus a 10f capacitor would require a 250s rise time, limiting the charging current to about 200ma. a pplica t ions i n f or m a t ion
LTC3855 0 3855f pc board layout checklist when laying out the printed circuit board, the following checklist should be used to ensure proper operation of the ic. these items are also illustrated graphically in the layout diagram of figure 14. figure 15 illustrates the current waveforms present in the various branches of the 2-phase synchronous regulators operating in the continuous mode. check the following in your layout: 1. are the top n-channel mosfets m1 and m3 located within 1 cm of each other with a common drain con- nection at c in ? do not attempt to split the input de- coupling for the two channels as it can cause a large resonant loop. 2. are the signal and power grounds kept separate? the combined ic signal ground pin and the ground return of c intvcc must return to the combined c out (C) ter- minals. the v fb and i th traces should be as short as possible. the path formed by the top n-channel mosfet, schottky diode and the c in capacitor should have short leads and pc trace lengths. the output capacitor (C) terminals should be connected as close as possible to the (C) terminals of the input capacitor by placing the capacitors next to each other and away from the schottky loop described above. 3. do the LTC3855 v fb pins resistive dividers connect to the (+) terminals of c out ? the resistive divider must be connected between the (+) terminal of c out and signal ground. the feedback resistor connections should not be along the high current input feeds from the input capacitor(s). 4. are the sense + and sense C leads routed together with minimum pc trace spacing? the flter capacitor between sense + and sense C should be as close as possible to the ic. ensure accurate current sensing with kelvin connections at the sense resistor or inductor, whichever is used for current sensing. 5. is the intv cc decoupling capacitor connected close to the ic, between the intv cc and the power ground pins? this capacitor carries the mosfet drivers current peaks. an additional 1f ceramic capacitor placed immediately next to the intv cc and pgnd pins can help improve noise performance substantially. 6. keep the switching nodes (sw1, sw2), top gate nodes (tg1, tg2), and boost nodes (boost1, boost2) away from sensitive small-signal nodes, especially from the opposite channels voltage and current sensing feed- back pins. all of these nodes have very large and fast moving signals and therefore should be kept on the output side of the LTC3855 and occupy minimum pc trace area. if dcr sensing is used, place the top resistor (figure 2b, r1) close to the switching node. 7. ar e diffp and diffn leads routed together and correctly kelvin sensing the output voltage? 8. use a modifed star ground technique: a low imped- ance, large copper area central grounding point on the same side of the pc board as the input and output capacitors with tie-ins for the bottom of the intv cc decoupling capacitor, the bottom of the voltage feedback resistive divider and the sgnd pin of the ic. pc board layout debugging start with one controller at a time. it is helpful to use a dc-50mhz current probe to monitor the current in the inductor while testing the circuit. monitor the output switching node (sw pin) to synchronize the oscilloscope to the internal oscillator and probe the actual output voltage as well. check for proper performance over the operating voltage and current range expected in the application. the frequency of operation should be maintained over the input voltage range down to dropout and until the output load drops below the low current operation thresholdtypically 10% of the maximum designed cur- rent level in burst mode operation. the duty cycle percentage should be maintained from cycle to cycle in a well-designed, low noise pcb implemen- tation. variation in the duty cycle at a subharmonic rate can suggest noise pickup at the current or voltage sensing inputs or inadequate loop compensation. overcompensa- tion of the loop can be used to tame a poor pc layout if regulator bandwidth optimization is not required. only after each controller is checked for its individual performance should both controllers be turned on at the same time. a particularly diffcult region of operation is when one controller channel is nearing its current comparator trip point when the other channel is turning on its top mosfet. a pplica t ions i n f or m a t ion
LTC3855 3855f figure 15. branch current waveforms r l1 d1 l1 sw1 r sense1 v out1 c out1 v in c in r in r l2 d2 bold lines indicate high switching current. keep lines to a minimum length. l2 sw2 3855 f15 r sense2 v out2 c out2 figure 14. recommended printed circuit layout diagram c b2 c b1 c intvcc + c in d1 1 f ceramic m1 m2 m3 m4 d2 + c vin v in r in l1 l2 c out1 v out1 gnd v out2 3855 f14 + c out2 + r sense r sense r pu2 pgood v pull-up f in 1 f ceramic i th1 v fb1 sense1 + sense1 ? freq sense2 ? sense2 + v fb2 i th2 tk/ss2 tk/ss1 pgood sw1 boost1 bg1 v in pgnd extv cc intv cc bg2 boost2 sw2 tg2 sgnd i lim mode/pllin run1 run2 clkout LTC3855 diffout tg1 diffn diffp a pplica t ions i n f or m a t ion
LTC3855 3855f this occurs around 50% duty cycle on either channel due to the phasing of the internal clocks and may cause minor duty cycle jitter. reduce v in from its nominal level to verify operation of the regulator in dropout. check the operation of the undervoltage lockout circuit by further lowering v in while monitoring the outputs to verify operation. investigate whether any problems exist only at higher out- put currents or only at higher input voltages. if problems coincide with high input voltages and low output currents, look for capacitive coupling between the boost, sw, tg, and possibly bg connections and the sensitive voltage and current pins. the capacitor placed across the current sensing pins needs to be placed immediately adjacent to the pins of the ic. this capacitor helps to minimize the effects of differential noise injection due to high frequency capacitive coupling. if problems are encountered with high current output loading at lower input voltages, look for inductive coupling between c in , schottky and the top mosfet components to the sensitive current and voltage sensing traces. in addition, investigate common ground path voltage pickup between these components and the sgnd pin of the ic. design example as a design example for a two channel high current regula- tor, assume v in = 12v(nominal), v in = 20v(maximum), v out1 = 1.8v, v out2 = 1.2v, i max1,2 = 15a, and f = 400khz (see figure 16). the regulated output voltages are determined by: v out = 0.6v ? 1 + r b r a ? ? ? ? ? ? using 20k 1% resistors from both v fb nodes to ground, the top feedback resistors are (to the nearest 1% standard value) 40.2k and 20k. the frequency is set by biasing the freq pin to 1v (see figure 12). the inductance values are based on a 35% maximum ripple current assumption (5.25a for each channel). the highest value of ripple current occurs at the maximum input voltage: l v i v v out l max out in max = ? ? ? ? ? ? ? f ? ( ) ( ) ? 1 channel 1 will require 0.78h, and channel 2 will require 0.54h. the vishay ihlp4040dz-01, 0.56h inductor is chosen for both rails. at the nominal input voltage (12v), the ripple current will be: ? i v l v v l nom out out in nom ( ) ( ) ? = ? ? ? ? ? ? ? f 1 channel 1 will have 6.8a (46%) ripple, and channel 2 will have 4.8a (32%) ripple. the peak inductor current will be the maximum dc value plus one-half the ripple current, or 18.4a for channel 1 and 17.4a for channel 2. the minimum on-time occurs on channel 2 at the maximum v in , and should not be less than 90ns: t on(min) = v out v in(max) f = 1.2v 20v(400khz) = 150ns with i lim foating, the equivalent r sense resistor value can be calculated by using the minimum value for the maximum current sense threshold (45mv). r sense(equiv) = v sense(min) i load(max) + ? i l(nom) 2 the equivalent required r sense value is 2.4m? for chan- nel 1 and 2.6m? for channel 2. the dcr of the 0.56h inductor is 1.7m? typical and 1.8m? maximum for a 25c ambient. at 100c, the estimated maximum dcr value is 2.3m?. the maximum dcr value is just slightly under the equivalent r sense values. therefore, r2 is not required to divide down the signal. for each channel, 0.1f is selected for c1. r1 = l (dcr max at 25 c) ? c1 = 0.56 h 1.8m ? ? 0.1 f = 3.11k choose r1 = 3.09k a pplica t ions i n f or m a t ion
LTC3855 3855f a pplica t ions i n f or m a t ion the power loss in r1 at the maximum input voltage is: p loss r1 = (v in(max) ? v out ) ? v out r1 the resulting power loss for r1 is 11mw for channel 1 and 7mw for channel 2. the sum of the sense resistor and dcr is 2.5m (max) for the r sense application whereas the inductor dcr for the dcr sense application is 1.8m (max). as a result of the lower conduction losses from the switch node to v out , the dcr sensing application has higher effciency. the power dissipation on the topside mosfet can be easily estimated. choosing a renesas rjk0305dpb figure 17. dcr sense effciency vs r sense effciency load current (a) 0 85 efficiency (%) power loss (w) 90 161412108642 80 75 70 95 4 3 2 1 0 5 3855 f17 1.2v r sense 1.2v dcr sense 1.8v r sense 1.8v dcr sense v in = 12v mode = ccm dcr sense app: see figure 16 r sense app: see figure 19 efficiency power loss figure 16. high effciency dual 400khz 1.8v/1.2v step-down converter d3 d4 m1 m2 0.1f 40.2k 1% l1 0.56h 3.09k 1% 1nf 150pf 0.1f 0.1f 82f 25v c out1 330f s2 l1, l2: vishay ihlp4040dz-01, 0.56h m1, m3: renesas rjk0305dpb m2, m4: renesas rjk0330dpb 20k 1% 12.1k 1% v out1 1.8v 15a m3 m4 0.1f l2 0.56h 1nf 150pf c out2 330f s2 20k 1% 4.99k 1% 100k 1% v out2 1.2v 15a tg1 tg2 boost1 boost2 sw1 sw2 bg1 bg2 sgnd pgnd freq sense1 + sense2 + diffp sense1 ? sense2 ? v fb1 v fb2 i th1 i th2 v in pgood intv cc tk/ss1 tk/ss2 v in 4.5v to 20v 3855 f16 extv cc 0.1f 0.1f LTC3855 mode/pllin i lim1 itemp1 itemp2 i lim2 diffn diffout clkout run1 run2 3.09k 1% 4.7f 1f 2.2 + + 10f 25v s2 + 20k, 1%
LTC3855 3855f a pplica t ions i n f or m a t ion mosfet results in: r ds(on) = 13m? (max), v miller = 2.6v, c miller ? 150pf. at maximum input voltage with t j (estimated) = 75c: p main = 1.8v 20v 15a ( ) 2 1+ (0.005)(75 c ? 25 c) [ ] ? 0.013 ? ( ) + 20v ( ) 2 15a 2 ? ? ? ? ? ? 2 ? ( ) 150pf ( ) ? 1 5v ? 2.6v + 1 2.6v ? ? ? ? ? ? 400khz ( ) = 329mw + 288mw = 617mw for a 2m sense resistor, a short-circuit to ground will result in a folded back current of: i sc = 1/ 3 ( ) 50mv 0.002 ? ? 1 2 90ns(20v) 0.56 h ? ? ? ? ? ? = 6.7a a renesas rjk0330dpb, r ds(on) = 3.9m?, is chosen for the bottom fet. the resulting power loss is: p sync = 20v ? 1.8v 20v 15a ( ) 2 ? 1+ 0.005 ( ) ? 75 c ? 25 c ( ) ? ? ? ? ? 0.0039 ? p sync = 1w c in is chosen for an rms current rating of at least 7.5a at temperature assuming only channel 1 or 2 is on. c out is chosen with an equivalent esr of 4.5m? for low output ripple. the output ripple in continuous mode will be highest at the maximum input voltage. the output voltage ripple due to esr is approximately: v oripple = r esr (?i l ) = 0.0045? ? 6.8a = 31mv pCp further reductions in output voltage ripple can be made by placing a 100f ceramic across c out . l1, l2: vishay ihlp5050ce-01, 0.68h c out1 , c out3 : murata grm32er60j107me20 c out2 , c out4 : kemet t520v337m004ate009 rntc1, rntc2: murata ncp18wf104j03rb 3855 f18 tg1 boost1 pgnd1 bg1 v in intv cc extv cc bg2 pgnd2 boost2 tk/ss1 i th1 v fb1 sgnd v fb2 i th2 tk/ss2 sense2 + sense2 ? diffp 20k 0.1f 40.2k sense1 ? sense1 + run1 itemp1 itemp2 freq mode/pllin phsasmd clkout sw1 diffn diffout run2 i lim1 i lim2 pgood1 pgood2 pgood1 pgood2 nc sw2 tg2 63.4k 49.9k r ntc1 100k 20k 86.6k 100k 100k 20k 2.2 4.7f 0.1f 0.1f LTC3855 1nf 20k 0.1f 100pf 10f s2 82f 25v s2 1nf 15k 0.1f 100pf 0.1f 49.9k r ntc2 100k 20k cmdsh-3 m4 rjk0330dpb m3 rjk0305dpb m2 rjk0330dpb m1 rjk0305dpb cmdsh-3 0.1f l1 0.68h l2 0.68h 24.9k 24.9k 3.01k 3.01k v out2 1.8v 15a v in 4.5v to 20v v out1 2.5v 15a + c out1 100f 6.3v c out2 330f 4v s2 + c out3 100f 6.3v c out4 330f 4v s2 + figure 18. 2.5v, 15a and 1.8v, 15a supply with ntc temperature compensated dcr sensing, f sw = 350khz typical a pplica t ions
LTC3855 3855f typical a pplica t ions figure 19. 1.8v, 15a and 1.2v, 15a supply, f sw = 400khz l1, l2: vitec 59pr9875 c out1 , c out3 : murata grm31cr60j107me39l c out2 , c out4 : sanyo 2r5tpe330m9 3855 f19 tg1 boost1 pgnd1 bg1 v in intv cc extv cc bg2 pgnd2 boost2 tk/ss1 i th1 v fb1 sgnd v fb2 i th2 tk/ss2 sense2 + sense2 ? diffp 20k 1nf 20k sense1 ? sense1 + run1 itemp1 itemp2 freq mode/pllin phsasmd clkout sw1 diffn diffout run2 i lim1 i lim2 pgood1 pgood2 pgood1 pgood2 nc sw2 tg2 40.2k 100k 100k 100k 20k 2.2 4.7f 0.1f 0.1f LTC3855 1nf 18k 0.1f 150pf 10f s2 82f 25v s2 1.5nf 5.49k 0.1f 150pf 1nf cmdsh-3 m4 rjk0330dpb m3 rjk0305dpb m2 rjk0330dpb m1 rjk0305dpb cmdsh-3 0.1f l1 0.4h l2 0.4h 0.002 0.002 v out2 1.2v 15a v in 4.5v to 20v v out1 1.8v 15a + c out1 100f 6.3v c out2 330f 2.5v s2 + c out3 100f 6.3v c out4 330f 2.5v s2 + 100 100 100 100
LTC3855 3855f typical a pplica t ions figure 20. high effciency dual phase 1.2v, 40a supply, f sw = 250khz l1, l2: pulse pa0513.441nlt c out1 : murata grm31cr60j107me39l c out2 : sanyo 2r5tpe330m9 3855 f20 tg1 boost1 pgnd1 bg1 v in intv cc extv cc bg2 pgnd2 boost2 tk/ss1 i th1 v fb1 sgnd v fb2 i th2 tk/ss2 sense2 + sense2 ? diffp 20k 1nf 20k sense1 ? sense1 + run1 itemp1 itemp2 freq mode/pllin phsasmd clkout sw1 diffn diffout run2 i lim1 i lim2 pgood1 pgood2 pgood nc sw2 tg2 5.9k 100 250khz run run 100 100k 2.2 4.7f 0.1f 0.1f LTC3855 10f s4 270f 16v 100pf 2200pf 1nf cmdsh-3 m4 rjk0330dpb s2 m3 rjk0305dpb m2 rjk0330dpb s2 m1 rjk0305dpb cmdsh-3 0.1f l1 0.44h l2 0.44h 0.001 1% 0.001 1% v in 4.5v to 14v v out 1.2v 40a + c out1 100f 6.3v s4 c out2 330f 2.5v s4 + 100 100 0.1f
LTC3855 3855f figure 21. high effciency dual phase 1.2v, 40a supply with dcr sensing, f sw = 250khz l1, l2: vishay ihlp5050fd-01, 0.47h c out1 : murata grm31cr60j107me39l c out2 : sanyo 2r5tpe330m9 3855 f21 tg1 boost1 pgnd1 bg1 v in intv cc extv cc bg2 pgnd2 boost2 tk/ss1 i th1 v fb1 sgnd v fb2 i th2 tk/ss2 sense2 + sense2 ? diffp 20k 0.1f 20k sense1 ? sense1 + run1 itemp1 itemp2 freq mode/pllin phsasmd clkout sw1 diffn diffout run2 i lim1 i lim2 pgood1 pgood2 pgood nc sw2 tg2 10k 100k 2.2 4.7f 0.1f 0.1f LTC3855 10f s4 270f 16v 330pf 3300pf 0.1f cmdsh-3 m4 rjk0330dpb s2 m3 rjk0305dpb m2 rjk0330dpb s2 m1 rjk0305dpb cmdsh-3 1f l1 0.47h l2 0.47h 3.92k 3.92k v in 4.5v to 14v v out 1.2v 40a + c out1 100f 6.3v s4 c out2 330f 2.5v s4 + 0.1f typical a pplica t ions
LTC3855 3855f typical a pplica t ions figure 22. small size, dual phase 0.9v, 50a supply, f sw = 400khz l1, l2: vitec 59pr9873 c out1 : murata grm31cr60j107me39l c out2 : sanyo 2r5tpe330m9 3855 f22 tg1 boost1 pgnd1 bg1 v in intv cc extv cc bg2 pgnd2 boost2 tk/ss1 i th1 v fb1 sgnd v fb2 i th2 tk/ss2 sense2 + sense2 ? diffp 10k 1nf 20k sense1 ? sense1 + run1 itemp1 itemp2 freq mode/pllin phsasmd clkout sw1 diffn diffout run2 i lim1 i lim2 pgood1 pgood2 pgood nc sw2 tg2 5.1k 100 400khz 100k 100 100k 2.2 4.7f 0.1f 0.1f LTC3855 10f s4 270f 16v 220pf 2700pf 1nf cmdsh-3 m4 rjk0330dpb s2 m3 rjk0305dpb s2 m2 rjk0330dpb s2 m1 rjk0305dpb s2 cmdsh-3 1f l1 0.23h l2 0.23h 0.001 1% 0.001 1% v in 4.5v to 14v v out 0.9v 50a + c out1 100f 6.3v s2 c out2 330f 2.5v s4 + 100 100 0.1f
LTC3855 3855f typical a pplica t ions figure 23. triple phase 1v, 50a supply with auxillary 3.3v, 5a rail, f sw = 400khz tg1 boost1 pgnd1 bg1 v in intv cc extv cc bg2 pgnd2 boost2 tk/ss1 i th1 v fb1 sgnd v fb2 i th2 tk/ss2 sense2 + sense2 ? diffp 13.3k 1nf 20k sense1 ? sense1 + run1 itemp1 itemp2 freq mode/pllin phsasmd clkout sw1 diffn diffout run2 i lim1 i lim2 pgood1 pgood2 pgood1v nc sw2 tg2 2k 100 100k run1 run1 run2 100 100k 2.2 4.7f 0.1f 0.1f LTC3855 10f s3 270f 16v 330pf 4700pf 1nf cmdsh-3 m4 rjk0330dpb m3 rjk0305dpb m2 rjk0330dpb m1 rjk0305dpb cmdsh-3 1f l1 0.3h l2 0.3h 0.002 1% 0.002 1% v in 4.5v to 14v v out1 1v 50a + c out1 100f 6.3v s3 c out2 470f 2.5v s4 + 100 100 0.1f l1, l2, l3: vitec 59pr9874 l4: wurth 744311220 c out1 , c out3 : tdk c3225x5r0j107m c out2 : kemet t530d477m2r5ate006 3855 f23 tg1 boost1 pgnd1 bg1 v in intv cc extv cc bg2 pgnd2 boost2 tk/ss1 i th1 v fb1 sgnd v fb2 i th2 tk/ss2 sense2 + sense2 ? diffp 90.9k 0.1f 20k sense1 ? sense1 + run1 itemp1 itemp2 freq mode/pllin phsasmd clkout sw1 diffn diffout run2 i lim1 i lim2 pgood1 pgood2 pgood3.3v nc sw2 tg2 10k 100 run1 100k 100 100k 2.2 4.7f 0.1f 0.1f LTC3855 100pf 0.1f 3300pf 1nf cmdsh-3 m7 s4816bdy m6 rjk0330dpb m5 rjk0305dpb cmdsh-3 1f l3 0.3h 0.002 1% v out2 3.3v 5a c out3 100f 6.3v l4 2.2h 4.99k 2.49k 10f
LTC3855 0 3855f 0.1f 90.9k 1% l2 2.2h 1000pf 1000pf 1000pf 22f 50v 20k 1% 10k 1% v out1 3.3v 5a 0.1f 147k 1% l2 3.3h 1000pf c out2 150f 20k 1% 15k 1% 122k 1% v out2 5v 5a tg1 tg2 boost1 boost2 sw1 sw2 bg1 bg2 sgnd pgnd freq sense1 + sense2 + run2 extv cc sense1 ? sense2 ? v fb1 v fb2 i th1 i th2 v in pgood intv cc tk/ss1 tk/ss2 v in 7v to 24v 3855 f24 0.1f 100pf 0.1f LTC3855 mode/pllin i lim clkout run1 diffp diffn diffout 4.7f + c out1 220f + 10pf 15pf 100pf 10 10 10 10 2.2 1f d4 d3 l1: tdk rlf 7030t-2r2m5r4 l2: tdk ulf10045t-3r3n6r9 c out1 : sanyo 4tpe220mf c out2 : sanyo 6tpe150mi 8m 8m m1 m2 si4816bdy si4816bdy typical a pplica t ions figure 24. 3.3v/5a, 5v/5a converter using sense resistors
LTC3855 3855f typical a pplica t ions l1: wurth 7443551131 l2: wurth 7443551370 c out1 , c out2 : sanyo 16svpc39mv 3855 f25 tg1 boost1 pgnd1 bg1 v in intv cc extv cc bg2 pgnd2 boost2 tk/ss1 i th1 v fb1 sgnd v fb2 i th2 tk/ss2 sense2 + sense2 ? diffp 20k 0.1f 147k sense1 ? sense1 + run1 itemp1 itemp2 freq mode/pllin phsasmd clkout sw1 diffn diffout run2 i lim1 i lim2 pgood1 pgood2 pgood1 pgood2 nc sw2 tg2 383k 100k 100k 20k 2.2 4.7f 0.1f 0.1f LTC3855 5.6nf 10k 47pf 4.7f s6 100f 50v 5.6nf 4.99k 0.1f 0.1f 47pf 0.1f cmdsh-3 m4 bsc093n040ls m3 bsc093n040ls m2 bsc093n040ls m1 bsc093n040ls cmdsh-3 0.1f l1 13h l2 3.7h 24k 24k 18k 8.2k v out2 5v 10a v in 13v to 38v v out1 12v 6a + c out1 39f 16v s2 + c out2 39f 16v s2 + figure 25. 12v, 6a and 5v, 10a supply with dcr sensing, f sw = 250khz
LTC3855 3855f p ackage descrip t ion fe package 38-lead plastic tssop (4.4mm) (reference ltc dwg # 05-08-1772 rev a) exposed pad variation aa 4.75 (.187) ref fe38 (aa) tssop 0608 rev a 0.09 ? 0.20 (.0035 ? .0079) 0o ? 8o 0.25 ref 0.50 ? 0.75 (.020 ? .030) 4.30 ? 4.50* (.169 ? .177) 1 19 20 ref 9.60 ? 9.80* (.378 ? .386) 38 1.20 (.047) max 0.05 ? 0.15 (.002 ? .006) 0.50 (.0196) bsc 0.17 ? 0.27 (.0067 ? .0106) typ recommended solder pad layout 0.315 0.05 0.50 bsc 4.50 ref 6.60 0.10 1.05 0.10 4.75 ref 2.74 ref 2.74 (.108) millimeters (inches) *dimensions do not include mold flash. mold flash shall not exceed 0.150mm (.006") per side note: 1. controlling dimension: millimeters 2. dimensions are in 3. drawing not to scale see note 4 4. recommended minimum pcb metal size for exposed pad attachment 6.40 (.252) bsc
LTC3855 3855f information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. p ackage descrip t ion 6.00 0.10 (4 sides) note: 1. drawing is a jedec package outline variation of (wjjd-2) 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.20mm on any side, if present 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package pin 1 top mark (see note 6) pin 1 notch r = 0.45 or 0.35 s 45 chamfer 0.40 0.10 4039 1 2 bottom view?exposed pad 4.50 ref (4-sides) 4.42 0.10 4.42 0.10 4.42 0.05 4.42 0.05 0.75 0.05 r = 0.115 typ 0.25 0.05 0.50 bsc 0.200 ref 0.00 ? 0.05 (uj40) qfn rev ? 0406 recommended solder pad pitch and dimensions apply solder mask to areas that are not soldered 0.70 0.05 4.50 0.05 (4 sides) 5.10 0.05 6.50 0.05 0.25 0.05 0.50 bsc package outline r = 0.10 typ uj package 40-lead plastic qfn (6mm 6mm) (reference ltc dwg # 05-08-1728 rev ?)
LTC3855 3855f linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com ? linear technology corporation 2009 lt 1009 ? printed in usa r ela t e d p ar t s part number description comments ltc3853 triple output, multiphase synchronous step-down dc/dc controller, r sense or dcr current sensing and tracking phase-lockable fixed 250khz to 750khz frequency, 4v v in 24v, v out3 up to 13.5v ltc3731 3-phase synchronous controller, expandable to 12 phases differential amp, high output current 60a to 240a phase-lockable fixed 250khz to 600khz frequency, 0.6v v out 5.25v, 4.5v v in 32v, ltc3850/ ltc3850-1/ ltc3850-2 dual 2-phase, high effciency synchronous step-down dc/ dc controller, r sense or dcr current sensing and tracking phase-lockable fixed 250khz to 780khz frequency, 4v v in 30v, 0.8v v out 5.25v ltc3854 small footprint wide v in range synchronous step-down dc/dc controller, r sense or dcr current sensing fixed 400khz operating frequency 4.5v v in 38v, 0.8v v out 5.25v, 2mm 3mm qfn-12 ltc3851a/ ltc3851a-1 no r sense ? wide v in range synchronous step-down dc/ dc controller, r sense or dcr current sensing and tracking phase-lockable fixed 250khz to 750khz frequency, 4v v in 38v, 0.8v v out 5.25v, msop-16e, 3mm 3mm qfn-16, ssop-16 ltc3878 no r sense constant on-time synchronous step-down dc/dc controller, no r sense required very fast transient response, t on(min) = 43ns, 4v v in 38v, 0.8v v out 0.9v in , ssop-16 ltc3879 no r sense constant on-time synchronous step-down dc/dc controller, no r sense required very fast transient response, t on(min) = 43ns, 4v v in 38v, 0.6v v out 0.9v in , msop-16e, 3mm 3mm qfn-16 ltm4600hv 10a dc/dc module ? complete power supply high effciency, compact size, fast transient response 4.5v v in 28v, 0.8v v out 5v, 15mm 15mm 2.8mm ltm4601ahv 12a dc/dc module complete power supply high effciency, compact size, fast transient response 4.5v v in 28v, 0.8v v out 5v, 15mm 15mm 2.8mm ltc3610 12a, 1mhz, monolithic synchronous step-down dc/dc converter high effciency, adjustable constant on-time 4v v in 24v, v out(min) 0.6v, 9mm 9mm qfn-64 ltc3611 10a, 1mhz, monolithic synchronous step-down dc/dc converter high effciency, adjustable constant on-time 4v v in 32v, v out(min) 0.6v, 9mm 9mm qfn-64 ltc3857/ ltc3857-1 low i q , dual output 2-phase synchronous step-down dc/dc controller with 99% duty cycle phase-lockable fixed operating frequency 50khz to 900khz, 4v v in 38v, 0.8v v out 24v, i q = 50a ltc3868/ ltc3868-1 low i q , dual output 2-phase synchronous step-down dc/dc controller with 99% duty cycle phase-lockable fixed operating frequency 50khz to 900khz, 4v v in 24v, 0.8v v out 14v, i q = 170a, lt3845 low i q , high voltage synchronous step-down dc/dc controller adjustable fixed operating frequency 100khz to 500khz, 4v v in 60v, 1.23v v out 36v, i q = 30a, tssop-16 no r sense is a trademark of linear technology corporation. module is a registered trademark of linear technology corporation.

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